N25Q128A13ESF40F NUMONYX, N25Q128A13ESF40F Datasheet - Page 41

• Manufacturer Part Number: N25Q128A13ESF40F
• Description: NUMN25Q128A13ESF40F 128MB SPI FLASH MEMO
• Manufacturer: NUMONYX

6.3.2
6.4
XIP Volatile Configuration bits (VCR bit 3)
The bit 3 of the Volatile Configuration Register is the XIP enabling bit, this bit must be set to
0 to enable the memory working on XIP mode. For devices with a feature set digit equal to 2
or 4 in the part number (Basic XiP), this bit is always Don't Care, and it is possible to operate
the memory in XIP mode without setting it to 0. See
Volatile Enhanced Configuration Register
The Volatile Enhanced Configuration Register (VECR) affects the memory configuration
after every execution of Write Volatile Enhanced Configuration Register (WRVECR)
instruction: this instruction overwrite the memory configuration set during the POR
sequence by the Non Volatile Configuration Register (NVCR). Its purpose is:
enabling of QIO-SPI protocol and DIO-SPI protocol
HOLD (Reset) functionality disabling
To enable the VPP functionality in Quad I/O modify operations
To define output driver strength (3 bit)
Warning:
WARNING: in case of both QIO-SPI and DIO-SPI enabled, the
memory works in QIO-SPI
Section 16: Ordering
information.
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