STA310 STMicroelectronics, STA310 Datasheet - Page 54

• Manufacturer Part Number: STA310
• Description: IC AUDIO DECODER 6+2CH 80-TQFP
• Manufacturer: STMicroelectronics
• Type: Audio Decoderr

Specifications of STA310

• Applications: HDTV, Players, Receivers, Set-Top Boxes
• Voltage - Supply, Analog: 2.5V
• Voltage - Supply, Digital: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP, 80-VQFP
• Audio Codec Type: MP3 Decoder
• No. Of Dacs: 3
• No. Of Input Channels: 2
• No. Of Output Channels: 6
• Adc / Dac Resolution: 32bit
• Sampling Rate: 192kHz
• Interface Type: I2C, Serial, Parallel
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8856; STA310

STA310
Description: These registers indicate which interrupt
occurred. Provided an interrupt is enabled through
the register INTE, if the corresponding bit of INT is
set, the corresponding interrupt has occurred. The
signal IRQ is activated whenever one of the bits of
INT become set. Depending on the nature of the con-
dition, clearing a bit in INT register is performed by ei-
ther reading the MSB of INT register, or by reading
the MSB of the associated condition registers (see
below). This register is reset by software reset.
The table below shows the interrupt nature indicated
by each bit..
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Numer
Bit
10
0
1
2
3
4
5
6
7
8
9
Name
HDR
DEM
PCM
SYN
ERR
BOF
ANC
SFR
PTS
FBF
FBE
Change in Synchronization Status
Valid Header Registered
Error Detected
Sampling frequency changed
De-emphasis Changed
First Bit of New Frame at Output
Stage
First Bit of New Frame with PTS at
Output Stage
Not implemented
PCM Output Underflow
Frame Buffer Full: The frame buffer
memory contains 2 frames: one
decoded, and one parsed for next
decoding
Frame Buffer Empty: The frame
buffer memory contains 1 frame
which begins to be decoded. The
next frame begins to be parsed
(2)
Condition Signalled
(2)
(1)
(2)
(2)
(1)
(2)
(1)
Notes: 1. Cleared when a reset occurs or when the MSB of the in-
9.11 Interrupt status registers
SYNC_STATUS
Synchronization status
Address: 0x40
Type: RO
Software Reset: UND
Hardware Reset: UND
Numer
Address
7
Bit
12
13
14
15
11
0x0F
0x40
0x41
0x42
0x46
2. Cleared when a reset occurs or when the MSB of the
3. Only available in STA310 cut 2.0
6
terrupt register is read
corresponding register is read. Affected registers are
listed in the following table
RST
LCK
Name
USD
TBD
FIO
5
(3)
(3)
ERROR
SYNCSTATUS
ANCCOUNT
HEAD 4
PTS [32]
FIFO Input has Overflowed
The STA310 has detected a change
in the incoming audio format. The
soft Reset produce must be applied
and the device must be re-initialized
according to the new audio format
detected. Registers DECODESEL
(0x4d) and STREAMSEL (0x4c)
contain the new audio format (1)
A break has occurred in the S/PDIF
stream causing the internal S/PDIF
PLL to get unlocked. The soft reset
procedure must be applied and the
device must be re-initialized
according to the current audio format
decoding contained in the registers
DECODESEL (0x4d) and
SRTREAMSEL (0x4c). (1)
Reserved
Reserved
4
3
Condition Signalled
PAC
Name
2
1
FRA
(2)
0