STA310 STMicroelectronics, STA310 Datasheet - Page 41

• Manufacturer Part Number: STA310
• Description: IC AUDIO DECODER 6+2CH 80-TQFP
• Manufacturer: STMicroelectronics
• Type: Audio Decoderr

Specifications of STA310

• Applications: HDTV, Players, Receivers, Set-Top Boxes
• Voltage - Supply, Analog: 2.5V
• Voltage - Supply, Digital: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP, 80-VQFP
• Audio Codec Type: MP3 Decoder
• No. Of Dacs: 3
• No. Of Input Channels: 2
• No. Of Output Channels: 6
• Adc / Dac Resolution: 32bit
• Sampling Rate: 192kHz
• Interface Type: I2C, Serial, Parallel
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8856; STA310

Address: 0x56
Type: R/W
Software Reset: NC
Hardware Reset: UND
Description:
The PCMCROSS register only acts if bit PFC of reg-
ister SPDIF_DTDI is set.
9.6 PDAC and PLL configuration registers
SFREQ
Sampling frequency
Address: 0x05
Type: R/WS
Software Reset: NC
Hardware Reset: 0
Description:
This status register holds the code of the current
sampling frequency. If the audio stream is encoded
(Dolby Digital, MPEG) or packetized (DVD_LPCM),
the sampling frequency is automatically read in the
audio stream and written into this register by the au-
dio DSP. The register is automatically updated by the
DSP when it performs a down-sampling (for exam-
ple, 96kHz to 48kHz).
The DSP resets SFREQ to 0.
For PCM stream or CDDA, this register is written to
by the application. The value in SFREQ corresponds
to the following frequencies:.
LRS[1:0]
CSW[1:0]
CLR[1:0]
VCR[1:0]
Bitfield
7
6
00: Left channel is mapped on the left
output, Right channel is mapped on the
Right output.
01: Left channel is duplicated on both
outputs.
10: Right channel is duplicated on both
outputs.
11: Right channel and Left channel are
toggled.
Cross left and right surround.
Cross centre and subwoofer.
Cross left and right channels.
These 2 bits manage the VCR outputs.
5
4
Description
3
2
1
0
PLLCTRL
PLL Control
Address: 0x12
Type: R/W
Software Reset: NA
Hardware Reset: 0x19
Description:
PLL_DATA
OCLK
[2:0]
SYSCLC
K[1:0]
(KHz)
(KHz)
Value
Value 10 11 12
Bitfield Value
Fs
Fs
7
16 -
46 44.1 32
6
0
-01
011
111
-00
010
110
0
1
2
3
1
5
12 11.025
Forbidden
from internal audio
PLL
Audio master Clock
from internal S/PDIF
receiver
System Clock from CLK pad
Output
System Clock from CLK pad divided
by 2
System Clock from internal system
PLL
System Clock from internal system
PLL divided by 2
Configure PCMCLK
source and direction
Audio master Clock
from PCMLCK pad.
Audio master Clock
from internal audio
PLL
Audio master Clock
from internal S/PDIF
receiver
Audio master Clock
2
SYSCLSCK[1..0]
13
Description
3
4
-
96 88.2 64
4
14 15 16
8
3
5
- 192 176.4 128 -
6
PCMCLK pad
direction
Input
Input
Input
Output
Output
2
OCLK[2..0]
7
-
17
STA310
24 22.05
1
8
18 19
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9
0