STA310 STMicroelectronics, STA310 Datasheet
STA310
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STA310 Summary of contents
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... Dolby Laboratories. DESCRIPTION The STA310 is a fully integrated Audio Decoder ca- pable of decoding all the above listed formats. Encoded input data can be entered either by a serial (I2S or SPDIF parallel interface. A second input data stream (I2S) is available for micro input ...
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... Handshake for the Data Transfer, aconfigurable by the SIN_SETUP register S) I Clock Input Data, active low I Serial Input Data I Word Clock for the Input O Handshake for the Data Transfer, active low I/O Oversampling Clock input for STA310 when generated externally O Bit Clock for the DAC Function ...
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... STA310 AUDIO DECODER PIN DESCRIPTION (continued) Pin Number Name 68 LRCLK 72 PCM_OUT0 73 PCM_OUT1 76 PCM_OUT2 77 PCM_OUT3 IEC958 Interface (S/PDIF) - One Output Port., One Input Ports. 58 I958OUT 25 SPDP 24 SPDN 26 SPDF 28 VDDA 29 GNDA STATUS INFORMATION PCM Related Information 54 SFREQ 57 DEEMPH Audio Video Synchronization 59 PTSB Other Signals ...
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... STA310 2 STA310 AUDIO DECODER PIN DESCRIPTION (continued) Pin Number Name 30 PLLSF Power and Ground GND VDD VDD3 Notes (1) Open Drain (2) Internal Pull-up (3) Tri-State PIN CONNECTION (Top view VDD 5 GND RS232RX 9 RS232TX VDD3 10 GND VDD 4/90 Type I External Filter For System PLL. ...
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... X in the source/sink current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability Parameters = 3.3V +/-0.3V 70° amb Parameters Conditions Vdd Vdd V<0V, V>Vdd Leakage <1 A Conditions STA310 Value Unit -0.5 to 3.3 -0.5 to (Vdd+0.5) -0 -0.5 to (Vdd+0.5) unless otherwise spec- Value Unit 2.5 -20 to 125 Min Typ ...
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... Symbol Parameters P Power Dissipation 2.4V DD INTRODUCTION The STA310 is a fully integrated multi-format audio decoder. It accepts as input, audio data streams coded with all the formats listed above. 2 I2S AC3 DVD Audio MPEG S/P DIF 2.1 Inputs and Outputs 2.1.1 Data Inputs - Through a parallel interface (shared with the control interface) - Through a serial interface (for all the I - Through a S/P DIF (SPDIF or IEC-61937 standards) ...
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... ARCHITECTURE OVERVIEW 3.1 Data flow The STA310 is based on a programmable MMDSP+ core optimized for audio decoding algorithms. Dedicated hardware has been added to perform specific operations such as bitstream depacking or IEC data formatting. The arrows in Figure 3 indicate the data flow within the chip. ...
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... The address bus A[7..0 used to select one of the 256 register locations. - The data bus DATA[7..0 read cycle is requested, the data lines D[7:0] will be driven by the IC. For a write cycle, the STA310 will latch the data placed on the data lines when the WAIT signal is driven high. ...
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... See in the Appendix X.x for I C message format examples. 3.5 Decoding process The decoding process in the STA310 is done in several stages: - Parsing, - Main decoding, - Post decoding, - Bass redirection, - Volume and Balance control. ...
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... OPERATION 4.1 Reset The STA310 can be reset either by a hardware reset software reset: - The hardware reset is sent when the pin RESET is activated low during at least 60ns. This is equiv- alent to a power-on reset. This resets all the configuration registers, i.e. PLL registers (PLLSYS, PLLPCM), Interrupt registers (INTE, INT, ERROR), interface registers (SIN_SETUP, CAN_SETUP) and command registers (SOFTRESET, RUN, PLAY, MUTE, SKIP_FRAME, REPEAT_FRAME) ...
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... Clocks There are two embedded PLLs in the STA310: the system PLL and the PCM PLL. The following is the block diagram of the system and audio clocks used in the STA310 Figure 3. PLL Block Diagram CLKOUT CLK / N sys_clockout sys_clk DSP Core Figure 4. Block Diagram of Functional PLL ...
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... STA310 4.2.1 System clock The system clock sent to the DSP core and the peripherals can be derived from 4 sources and the selection is performed through an Host Register; external clock, external clock divided by 2, internal system PLL and inter- nal system PLL divided by 2. ...
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... MUTE register is reset. The outputs are muted if the MUTE register is set stop decoding, the PLAY register should be reset. Resuming decoding is performed by writing PLAY to 1 again Init mode Run command Decoder ready to play sample Mute Clock (SCLK, LRCLK) State 0 Not running 1 Running STA310 Time Decode mode PCM Output 0 0 13/90 ...
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... STA310 Table 3. Decode Mode. Play and Mute commands effects Play Mute Note not possible to change configuration registers in this state necessary to soft reset the chip before. Only the following reg- isters can be changed “on-the-fly”: PCM_SCALE, BAL_LR, BAL_SUR, OCFG, DOWNMIX registers. 4.4 Data input interface description. ...
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... The register CAN_SETUP has 4 significant bits, and each bit has a specific meaning, see 41. Only the first byte is transferred to the STA310 because the number of time slots 4). SIN and LRCLKIN are sampled on the falling edge of DSTR In this case SIN_SETUP = 3 and CAN_SETUP = LeftFirstChannel + FallingStrobe + AllSlot = /33MHz, where the DSTR clock frequency, (max is 33 MHz) ...
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... SIN Transferred data Example 2: Only the first 2 bytes are transferred to the STA310 because the number of slots is 20 (16 + 4). SIN and LRCLKIN are sampled on the falling edge of DSTR. The data is in delayed mode. The register configuration is SIN_SETUP=3 and CAN_SETUP = DelayMode + LeftFirstChannel + FallingStrobe + AllSlot = ...
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... In this mode the data must be presented on the 8-bit parallel host data bus D[7..0]. Note that this bus is shared with the external controller. On the rising clock of DSTR the data byte is sampled by the STA310. The signal REQ is used to signal when the input FIFO is full. When REQ is de-asserted the transfer must be stopped to avoid data loss ...
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... SYNC_STATUS. 4.6 Decoding modes 4.6.1 AC-3 The STA310 is Dolby Digital certified for class A products. The decoder must be programmed so to specify the stream format as AC-3 encoded: register DECODESEL = 0. In the sections below are provided the modes specific to the AC-3 decoding. ...
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... The karaoke decoder is activated by the use of KARAMODE register, which specifies the downmix for the dif- ferent modes. This register replaces DOWNMIX register however possible to consider the incoming karaoke channels as any other multichannel stream and output it with a downmix specified in DOWNMIX reg- ister. For details, refer to the Digital Audio Compression AC-3 ATSC standard, annex C. STA310 19/90 ...
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... Output channel 1 on Left output, and channel 2 on Right output. This channels downmix is specified in the register DUALMODE. 4.6.2 MPEG The STA310 is able to decode MPEG-1 layerI and layerII encoded data, as well as MPEG-2 layer I, layer II data without extension (i.e. 2-channel streams). The MPEG input format should be specified in the DECODESEL register: - DECODESEL=1 for MPEG1 ...
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PCM/LPCM Data Data Input Interface Fifo 256 Bytes Packet Parser Frame Parser Frame Buffer Downsampling Filter 96kHz -> 48kHz Bass Redirection Volume, Balance Zeros Zeros PCM_OUT2 PCM_OUT0 PCM_OUT1 6-Channel AC-3 Data 2-Channel MPEG1/2 Data Data Input Interface Data Input ...
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... Pro Logic Decoding The STA310 can decode a 2-channel Pro Logic bitstream. The 2 channels could come from a CD player, an AC-3 2-channel bitstream or an MPEG1 bitstream. The 2-channel bitstream can be converted into a 4-channel output ( S). The surround (S) is simultaneously sent on Ls and Rs channels. A Pro Logic downmix en- ...
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... The bass redirection is performed after the Pro Logic decode. The same bass redirection configuration than those available in non-Pro Logic modes can be used except that the surround channels will not be added to the bass redirection. In the case of AC-3 or MPEG the STA310 is therefore capable of first decoding the AC-3 or MPEG stream then performing the Pro Logic decode. ...
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... STA310 STREAMSEL DECODESEL 4.9 How to Program a Post Processing 4.9.1 2 registers for the mode: PDEC (0x62) to define the type of PostProcessing PDEC 0x01 0x02 0x08 0x10 0x20 4.9 registers to control the “PostProcessing” Prologic decoder (PDEC = 0x01): PL ABL WS (0x64 DOWNMIX (0x65) 0,1 Remark: When playing “Dolby Digital Prologic encoded”, if PL_DOWNMIX is correctly set, Prologic decoder’ is automatically applied even if the register “ ...
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... Pro Logic program are band limited and bass is considered as leakage). Post Bass Volume Control Pcrocessing Management Post Pcrocessing Karaoke Channel Delay STA310 S/ Pdif Output PCM ( Left ,Right PCM (VCRs) Encoded Mute Off Post Pcrocessing Karaoke Channel Delay ...
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... STA310 Figure 14. PCM Output Configurations LFE Configuration 0 Not used with Prologic -16dB L -16dB C R -16dB -16dB LS RS -16dB LFE -6dB Configuration 2 5.2 PCM scaling PCM scaling is needed for every decoding mode (AC3, Pro Logic, MPEG, PCM applied at the end of the filtering steps before PCM output, allowing maximum effective word width for most of the signal processing be- fore ...
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... STA310 27/90 ...
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... STA310 How to read the above table: The first 4 columns list the possible configurations for output formats on the PCM outputs. The 5th column gives the description of the internal 24-bit decoded, scaled and rounded audio samples as they are stored in memory. These 24 bits are referred to as d23, d22,..., d0, where MSB=d23, LSB=d0. The last column describes the se- quence of bits that are output on PCM_OUT according to the selected format ...
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... Fs is the sampling frequency in kHz, Framesize is expressed in 16-bit words, Datarate is the bit rate in kbits per second. The latency insertion can not be disabled however it can be programmed to values different from those required in the standard by selecting the user-programmable-latency mode (by setting the bit 7 of IEC858_CONF regis- STA310 29/90 ...
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... STA310 ter). In this case, the latency is specified in the IEC958_LATENCY register. Note that there are minimum and maximum values to respect Table 7. AC-3 Min. Latency 256 1536 samples / Fs samples / Fs If those limits are not respected, an error interrupt occurs corresponding to error type: LATENCY_TOO_BIG, which automatically makes the chip switch to auto_latency mode. ...
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... In those cases, the decoder resets the corresponding parsing stage (packet or audio parser) then searches for the next correct frame. Miscellaneous errors: - LATENCY_TOO_BIG error indicates a problem of latency programming which is superior to the max- imum authorized value. Change the latency value or switch to auto-latency mode to solve the problem. Other miscellaneous errors are internally handled. STA310 31/90 ...
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... This signal, PTS, is used to signal the detection of a Presentation Time Stamp in a stream, for audio/video syn- chronization. When a PTS is detected, the signal PTS goes low during one LRCLK period generated while the PCM are output enable the use of an external counter to synchronize the STA310 with a video decod- er. ...
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... PLL_CMD(f) 0x12 18 PLL_ADD (f) 0xB5 181 ENA_ALL FRACPLL 0xB6 182 AU_PLL_FRACL_192 0xB7 183 AU_PLL_FRACH_192 0xB8 184 AU_PLL_XDIV_192 0xB9 185 AU_PLL_MDIV_192 0xBA 186 AU_PLL_NDIV_192 0xBB 187 AU_PLL_FRACL_176 0xBC 188 AU_PLL_FRACH_176 0xBD 189 AU_PLL_XDIV_176 0xBE 190 AU_PLL_MDIV_176 STA310 Name (a) (a) (b) (b) (b) (a) (a) 33/90 ...
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... STA310 Register function CHANNEL DELAY SETUP SPDIF OUTPUT SETUP COMMAND INTERRUPT INTERRUPT STATUS DECODING ALGORITHM SYSTEM SYNCHRONIZATION POST DECODING AND PRO LOGIC 34/90 HEX DEC 0x57 87 LDLY (1) 0x58 88 RDLY (1) 0x59 89 CDLY (1) 0x5A 90 SUBDLY 0x5B 91 LSDLY (1) 0x5C 92 RSDLY (1) 0x5D 93 UPDATE 0xAF 91 LVDLY ...
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... MP_DOWNMIX 0x76 118 MP_STATUS0 0x77 119 MP_STATUS1 0x78 120 MP_STATUS2 0x79 121 MP_STATUS3 0x7A 122 MP_STATUS4 0x7B 123 MP_STATUS5 0x6F 111 PN_DOWNMIX 0x68 104 PCM_BTONE STA310 Name (2) (2) (b) (b) (b) (b) (b) (b) (b) (b) (f) (f) (f) (f) (f) (f) (f) (f) (b) (b) (b) (b) (b) (b) (f) ...
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... STA310 Register function KARAOKE SECOND SERIAL INPUT LINEAR PCM (DVD AUDIO) REGISTERS LINEAR PCM (DVD VID & PCM) REGISTERS 36/90 HEX DEC 0x81 129 KAR_MCh0VOL 0x82 130 KAR_MCh1VOL 0x83 131 KAR_KEYCONT 0x84 132 KAR_KEYVALUE 0x85 133 KAR_VCANCEL 0x86 134 KAR_VVALUE 0x87 ...
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... LPCMV_DM_COEFT_12 0xA4 164 LPCMV_DM_COEFT_13 0xA8 168 LPCMV_CH_ASSIGN 0xA9 169 LPCMV_MULTI_CHS 0xB5 181 DEEMPH 0xAE 174 VCR_MIX 0xAF 175 VCR_LDLY 0xB0 176 VCR_RDLY 0x2B 43 BREAKPOINT 0x3A 58 CLOCKCMD 0xFF 255 INIT_RAM 0xE0 224 AUTODETECT_ENA 0xE1 225 AUTODETECT_SENS 0xE2 226 AUTODETECT_ALIGN STA310 Name 37/90 ...
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... Loading a patch into the STA310 will automatically change the register content. Please contact ST to have the correct value according to the patch being used. This register must be readonly after the STA310 has finished booting, in order to get a correct value (when INIT_RAM register hold the value 1) ...
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... STA310 cut 1.0, version number is : 0x10 - STA310 cut 2.0, version number is : 0x10 9.4 SETUP & INPUT REGISTERS The STA310 can get receive an input bitstream either from the I2s input or ffrom the Spdif input, the selec- tion and the configuration is done through 2 registers SIN_SETUP @ 12 and CAN_SETUP @ 13 ...
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... Address : 0x0E Type: WO Software Reset: NA Hardware Reset: NA Description: Data can be fed into the STa310 by using this register instead of the dedicated interface. there is no need to byte align the bitstream when using this register. 9.5 PCM CONFIGURATION RESISTERS PCMDIVIDER Divider for PCM clock ...
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... PLL 110 Audio master Clock Output from internal S/PDIF receiver 0 System Clock from CLK pad Output 1 System Clock from CLK pad divided System Clock from internal system PLL 3 System Clock from internal system PLL divided by 2 STA310 24 22. 41/90 ...
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... ENA_AU_FRACPLL Audio PLL Enable 7 Address: 0xB5 Type: R/W Software Reset: 1 Hardware Reset: 0 Description: This register is used to enable the audio PLL of the STA310. This register must be always set to “1” after either a soft or hardware reset. AU_PLL_FRACL_192 Frac Low Coefficient 7 Address: 0xB6 ...
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... Address: 0xBA Type: R/W Software Reset: 0x01 Hardware Reset: UND Description: This register must contain a NDIV value that enables the audio PLL to generate a frequency of ofact*192KHz for the PCMCK. Default value at soft reset assume: – Oversampling factor (ofact) = 384. PCMLCK = STA310 MDIV NDIV ...
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... STA310 384 x SF (where SF is the sampling frequency) – External crystal provide a clock running at 27MHz AU_PLL_FRACL_176 Frac Low Coefficient FRACL Address: 0xBB Type: R/W Software Reset: 0x3 Hardware Reset: UND Description: This register must contain a FRACL value that en- ables the audio PLL to generate a frequency of ofact*176KHz for the PCMCK ...
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... This register is used to signal when the STA310 has finished to boot. After a soft reset or a hardware re- set, the host processor must wait until INIT_RAM hold the value “1”. The host can then start to configure the STA310 ac- cording to its application. PLLMASK PCMCLK mask for half sampling frequency ...
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... STA310 Delay on left channel, expressed in number of group of 16 samples. LDLY = delay (ms (kHz RDLY Right channel delay Address: 0x58 Type: R/W Software Reset: NC Hardware Reset:UND Delay on right channel, expressed in number of group of 16 samples. RDLY = delay (ms)*Fs (kHz)/16 CDLY Centre channel delay Address: 0x59 ...
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... DSP will keep the delay values set previously) 1: The delay values held in the audio delay registers are updated in the DSP (i.e. the DSP will use the new values). This bit is automatically reset to zero after it the update has been carried out. Set to “0” SPDIF_MODE[1: STA310 0 47/90 ...
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... STA310 Address: 0x5F Type: R/W Software Reset: NC Hardware Reset: UND Description: The table below defines the category codes, values not listed are reserved. Category code General Experimental Reserved Solid State Memory Broadcast reception of dig. audio Broadcast reception of dig. audio Broadcast reception of dig. audio Broadcast reception of dig ...
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... Software Reset: NC Hardware: Reset UND Description: Description SPDIF_LATENCY register is used. Mode Description DAC_PCMCLK = 384Fs, DAC is 16-bit mode DAC_PCMLK = 256 Fs, DAC is 16-bit mode DAC_PCMLK = 384 Fs, DAC is 32-bit mode DAC_PCMLK = 256 Fs, DAC is 32-bit mode SFR STA310 IEC Divider Value PRE COP COM 49/90 ...
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... STA310 This register is used to set the value of the status bit in the IEC958 data stream. Bitfield COM Compress data bit. 1: compressed mode 0: non compressed mode. COP 1: copy allowed 0: copy not allowed PRE 1: output has pre-emphasis 0: output does not have pre-emphasis SFR 0000: if sampling frequency = 44.1KHz ...
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... Description: The feature is only available for STA310 cut 2.0. This register is used to enable the autodetection on the S/ PDIF. When high, the autodetection is present. When low, autodetection is disable. The STA310 cut 2.0 is able to detect the following au- dio format changes on the S?PDIF input The host must respond to the RST and LCK interrupt in order for the STA310 to take into account the change of the audio format ...
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... STA310 The feature is only available for STA310 cut 2.0. This register is used to configure the Left/Right sample alignement of the S/PDIF. Typical value is 10 9.9 Audio command registers SOFTRESET Soft reset Address: 0x10 Type: W0 Software Reset: NA Hardware: Reset: NA Description: When bit 0 of this register is set, a soft reset occurs. ...
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... Type: R/W Software Reset: 0 Hardware Reset: 0 Description: This register is used to enable each interrupt inde- pendently. Setting a bit in the register enables the corresponding interrupt. INT Interrupt @0x0A @0x09 Address: 0x0A - 0x09 Type: RO Software Reset: 0 Hardware Reset INTE[15:8] INTE[7: INTE[15:8] INTE[7:0] STA310 53/90 ...
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... TBD Notes: 1. Cleared when a reset occurs or when the MSB of the in- terrupt register is read 2. Cleared when a reset occurs or when the MSB of the corresponding register is read. Affected registers are listed in the following table 3. Only available in STA310 cut 2.0 Address (2) 0x0F 0x40 0x41 0x42 0x46 9 ...
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... In all other types of frame HEAD4[2:0] = “000” HEAD3 HEADER 3 register 7 0 Address: 0x43 Type: RO Software Reset: UND Hardware Reset: UND BSMOD Description depend on the type Description BSMOD if an Dolby Digital frame Description 0 DR=1 Dynamic range exists K=0 in normal mode, K=1 in Karaoke mode DTYPE STA310 the 1 0 55/90 ...
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... STA310 This register contains HEAD[23:16].HEAD3[7:5]=“000”, HEAD3[4:0] = DTYPE DTYPE is the data type and is defined as follows: Bit Description DTYPE 0000: Null data or Linear PCM 0001: Dolby Digital 0100: MPEG-1 Layer I 0101: MPEG-1 Layer II or MPEG-2 word extension 0110: MPEG-2 Layer II with extension ...
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... Decoding algorithm registers 38 The table below shows how the STREAMSEL and 39 DECODSEL registers should be programmed for dif- ferent types of bitstream Table 9. 42 STREAMSEL and DECODESEL programming 44 definitions 45 STREAMSEL DECODSEL (0x4C STA310 Value (decimal Mode (0x4D) 0 MPEG2 PES carrying Dolby Digital (ATSC) 1 ...
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... STA310 1 2 MPEG2 PES carrying MPEG2 frames for DVD video 1 3 MPEG2 PES carrying linear PCM for DVD video 2 1 MPEG1 packet carrying MPEG1 audio 3 0 Dolby Digital frames elementary streams 3 1 MPEG1 frame elementary streams 3 2 MPEG2 frame elementary stream ...
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... Max value = 3; min value = 0. SYNC_LOCK = 0, the audio parser is syn- chronized when it has detected one audio synchro word. SYNC_LOCK = n > 0, when the audio parser has detected one synchro word, it waits until it de- tects n supplementary audio sync words STA310 59/90 ...
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... STA310 When it has detected (SYNC_LOCK+1) sync words, it sends the data to the decoder. 9.14 Post decoding and pro logic registers PDEC1 Post decoder register VMAX DEM DCF DB PVIRT MPEG_DR PL Address: 0x62 Type: R/W Software Reset: NC Hardware Reset: UND Description: This register controls the post decoder operations. ...
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... If sub-woofer is not output LP(C) + LFE LP(C) + LFE LFE LFE. Simplified configuration. Low frequencies are exrtacted from C, Ls, Rs and LFE. If subwoofer is output, SUB = LP(C+Ls+Rs) + LFE sub-woofer is not output, SUB = LFE (C+Ls+Rs (C+Ls+Rs). BYPASS, All channels are directly routed to PCM outputs. configuration 1 without filters. DWSMODE Description STA310 61/90 ...
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... STA310 Downsampling filter Address: 0x70 Type: R/W Software Reset: NC Hardware Reset: UND Description: This register controls the downsampling filter for the LPCM video, LPCM audio modes. When decoding a 96kHz DVD-LPCM stream, it might be necessary to downsample the stream to 48kHz . Value Mode 0 Automatic (according to bitstream) ...
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... In custom A mode, the dialog normalization function is not done by the audio decoder, it has to be done by an external analog part. In all other modes CHAN_IDX the normalization is done by audio decoder. Value VOLUME0 and CHAN_IDX 3 CHAN_IDX value is automatically Meaning Custom A (Analog) Custom D (Digital) Line Out RF Mode STA310 63/90 ...
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... STA310 AC3_HDR High dynamic range Address: 0x6A Type: R/W Software Reset: NC Hardware Reset: UND Description: This register corresponds to the Dynamic range scale factor for high level signals, also called cut fac- tor in the Dolby specifications. HDR = 255 * Cut Factor (in decimal), where the cut factor is a fractional number between 0 and 1 ...
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... Address: 0x6F Type: R/W Software Reset: NC Hardware Reset: UND Description:. Value Note: in notation, 3/2 represents 3 front speakers and 2 surround speakers. AC3_STATUS0 STA310 after downmix performed enables Mono downmix AC3_DUALMODE = 3. Description Description 2/0 Dolby Surround (LT, RT) 1/0 (C) 2/0 (L, R) 3 3/1 ( 2/2 ( Dolby Phantom Mode ...
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... STA310 Dolby Digital status register Not used fs_cod AudioBaseAddress + 0x76 Type: RO Software Reset: NC Hardware Reset:UND Description: This register contains bit stream information extract- ed from the stream. Bitfield Description Bitrate code Code identifying the bitrate. Bitrate[4..0] = frmsizecod[5..1] fs_cod Code identifying the sampling frequency ...
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... Channel skip 7 Address : 0x68 Type: R/W Software Reset: 0x00 Hardware Reset: UND Description Mix level Description Audprodie: if set, indicates that room type and mix level are provided If audprodie is set, mix level indicates the sound level sound level Reserved STA310 0 Audprodie 1 0 67/90 ...
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... STA310 When this register is set to 1, the LFE channel is skipped. When this register is set to 0 the LFE chan- nel is decoded (if present). MP_PROG_NUMBER Program number Reserved Address: 0x69 Type: R/W Software Reset: 0x00 Hardware Reset: UND Description: When the stream is in Second Stereo mode, this reg- ister specifies which program is played ...
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... Capable 0.707 G V2 OFF 0.707 Capable: V1 OFF, 0.707 A2 + 0.707 0.707 Capable: V1 OFF, 0.707 G V2 OFF 0.707 A1 + 0.707 G, Capable 0.707 A1 + 0.707 G V2 OFF (Dolby Digital like 0.707 A2 + 0.707 G, Capable: V1 OFF 0.707 A2 + 0.707 (Dolby Digital like 0.707 A1 Capable 0.707 STA310 ...
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... STA310 0x1B 3/0 Karaoke 0.707 A1 Capable OFF 0x1C 3/0 Karaoke Capable: V1 OFF, 0.707 0x1D 3/0 Karaoke Capable: V1 OFF, V2 OFF 0x1E 3/0 Karaoke A1 Capable: V1 ON, V2 OFF (Dolby Digital like) 0x1F 3/0 Karaoke A2 Capable: V1 OFF (Dolby Digital like) MP_STATUS0 MPEG status register 0 ...
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... Center channel contains pink noise 0: Center channel is forced to zero 1: LFE channel contains pink noise 0: LFE channel is forced to zero 1: Left surround channel contain pink noise 0: Left surround channel is forced to zero 1: Right surround channel contains pink zero 0: Right surround channel is forced to zero DECODSEL registers STA310 71/90 ...
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... STA310 Type: R/W Software Reset: 0 Hardware Reset: UND Description: The value in this register sets the PCM beep tone fre- quency according to the formula: Beep_tone_frequency = (Fs/2)/(Register_value+1) 9.20 Karaoke registers This section describes the registers which select the karaoke effects, for example: volume, chorus, echo, reverb and mute ...
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... Voice channel 1 (R) volume 7 Address: 0x89 Type: R/W Reset value: 0xFF Description: This register KAR_MCh0VOL for the right voice channel instead of the left music channel Reserved Description 0: not muted, 1: muted Value has the same function Value has the same function STA310 1 0 MUTE 73/90 ...
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... STA310 KAR_DUET Duet ON/OFF switch Reserved Address: 0x8A Type: R/W Reset value: 0 Description: The value in this register sets the duet function on or off. When selected, the duet function is configured by register KAR_DUETTHRESH. Bitfield Description DUET 0: duet off and 1: duet on KAR_DUETTHRESH Duet threshold control ...
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... When the partial reset is finished, KAR_MODE[1:0] is automatically set to ’01’. 11: Total Software reset. The program is reset and the registers values are changed back to their reset default values CLK_P WS[1:0] DINEN OL OL STA310 75/90 ...
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... STA310 the handling of the second input. Bitfield Description DINEN DIN enable: 0: disabled, 1: enabled WS[1:0] PCM precision: 00: 16-bit mode, 01: 18-bit mode, 10: 20-bit mode, 11: 24-bit mode CLK_POL 0: Data and WS change on clockalling edge 1: Data and WS change on clockising edge WS_POL 0: Left data word = WS low, right data word ...
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... Type: R/W Software Reset: NC Hardware Reset: UND Description: This register sets the mixing gain for Lf to Lmix. See the note after register LPCMA_DM_COEFT_3 Downmix gain coefficients Address : 0x9A Type: R/W Software Reset PH_2R PH_3R PH_4R PH_5R Reserved COEF_0L COEF_0R STA310 77/90 ...
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... STA310 Hardware Reset: UND Description: This register sets the mixing gain for Lf to Rmix. See the note after register LPCMA_DM_COEFT_4 Downmix gain coefficients COEF_1L Address: 0x9B Type: R/W Software Reset: NC Hardware Reset: UND Description: This register sets the mixing gain for Rf to Lmix. See the note after register < ...
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... LPCMA_STATUS1 Linear PCM (DVD audio) status register 7 QUANTIZATION_WORD_L ENGTH_1[3: COEF_5R -(COEF_xL/30) 0<COEF_xL 199 -((COEF_xL - 100)/30) 200<COEF_xL 254 alpha[ COEF_xL 255 STERE DWNMX DOWN_MIX_CODE O_PB _VALID [3:0] Bitfield Description Identifying code DOWN_MIX_CODE valid Stereo playback mode Emphasis flag QUANTIZATION_WORD_L ENGTH_2[3:0] STA310 79/90 ...
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... STA310 Address: 0x77 Type: RO Software Reset: NC Hardware Reset: UND Description: This register contains bit stream information extract- ed from the stream. Bitfield QUANTIZATION_WORD Quantization word length for _LENGTH_2[3:0] group 2 QUANTIZATION_WORD Quantization word length for _LENGTH_1[3:0] group 1 LPCMA_STATUS2 Linear PCM (DVD audio) status register ...
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... Rmix. The input signal is inverted when PH_xR = ’0’ and non-inverted when ’1’. LPCMV_DM_COEFT_2 Downmix gain coefficients 2 For details see register 0x99 LPCMV_DM_COEFT_3 Downmix gain coefficients 3 For details see register 0x9A LPCMV_DM_COEFT_4 Downmix gain coefficients 4 For details see register 0x9B STA310 81/90 ...
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... STA310 LPCMV_DM_COEFT_5 Downmix gain coefficients 5 For details see register 0x9C PCMV_DM_COEFT_6 Downmix gain coefficients 6 For details see register 0x9D LPCMV_DM_COEFT_7 Downmix gain coefficients 7 For details see register 0x9E LPCMV_DM_COEFT_8 Downmix gain coefficients 8 For details see register 0x9F LPCMV_DM_COEFT_9 Downmix gain coefficients 9 ...
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... Description This register configures the multi channel structure for the output channels: 0: Stereo 1: Multi channels SU_P MA_S MS_C Description 1: Check of ’Restart_Header_CRC’ enable 1: Check of ’Major_Sync_CRC’ enable 1: Check of ’Max_Shift’ enable 1: Check of ’Substream_Parity’ enable DWNMIX[7:0] STA310 1 0 RH_C 1 0 83/90 ...
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... STA310 Description: This register controls the MLP downmix. Bitfield Description DWNMIX 0x00: 2 [7:0] (a) 0x01: 2/0 (Lo / Ro) (according to bitstream0) 0x02: 3/0 ( 0x03: 2/1 ( 0x04: 3/1 ( 0x05: 2/2 (L, R, Ls, Rs) 0x06: 3/3 ( Ls, Rs) For all other values there is no downmix. (a) Downmix 1/0 (one channel only) is ...
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... Description 00: none, 01: 50/15µs, 10: reserved, 11: CCITT J. STEREO PRL reserved COPY 3D_VCR STA310 1 0 D[1:0] 0 85/90 ...
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... STA310 Address: 0xAE Type: R/WS?? Software Reset: NC Hardware Reset: 0 Description: Bitfield Description 3D_VCR This bit selects "3-D sound" on the VCR channels using SRS processing (depending on the PDEC registers and ): 0: Standard sound (disable "3-D sound"), 1: Enable "3-D sound". COPY This bit is used to copy "Left/Right" ...
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... STA310 according to its application APPENDIX A OVERVIEW OF THE CHIP This STA310 is based on a very high performances low power general purpose DSP core, MMDSP+, and a set of dedicated peripherals. Internal audio and system PLL allows to configure the chip for a wide range of audio frequencies and DSP processing power (1 to 100 Mips) ...
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... RAM area bits) area of specific registers. - The two PLLs (Audio PLL and System PLL) can be controlled by the DSP itself (thru the MMIO bus the external world of the STA310 (thru the I2C Slave I/F or the Host parallel I/F). 88/90 ...
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... PIN 1 IDENTIFICATION 80 1 inch TYP. MAX. MECHANICAL DATA 0.063 0.006 0.055 0.057 0.013 0.015 0.008 0.630 0.551 0.295 0.0256 0.630 0.551 0.486 0.024 0.030 0.0393 (14x14x1.40mm TQFP80L STA310 OUTLINE AND TQFP80 A1 0.10mm .004 Seating Plane E Gage plane 0.25mm 89/90 ...
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... STA310 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...