DS33R41+ Maxim Integrated Products, DS33R41+ Datasheet - Page 9

• Manufacturer Part Number: DS33R41+
• Description: IC TXRX ETHERNET MAP 400-BGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS33R41+

• Number Of Drivers/receivers: 4/4
• Protocol: T1/E1/J1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers
1 DESCRIPTION
The DS33R41 provides interconnection and mapping functionality between Ethernet packet systems and T1/E1/J1
WAN time-division multiplexed (TDM) systems. The device is composed of a 10/100 Ethernet MAC, packet arbiter,
committed information rate controller (CIR), HDLC/X.86 (LAPS) mapper, SDRAM interface, control ports, four bit
error-rate testers (BERTs), and four integrated T1/E1/J1 transceivers. The packet interface consists of an MII/RMII
Ethernet PHY interface. The Ethernet interface can be configured for 10Mbps or 100Mbps service. The DS33R41
encapsulates Ethernet traffic with HDLC or X.86 (LAPS) encoding to be transmitted over up to four T1, E1, or J1
lines. The T1/E1/J1 interfaces also receive encapsulated Ethernet packets and transmit the extracted packets over
the Ethernet ports. Access is provided between the serial port and the integrated T1/E1/J1 transceivers to the
intermediate signal bus that is based on the Dallas Semiconductor integrated bus operation (IBO), running at
8.192Mbps.
The device includes four software-selectable T1, E1, or J1 transceivers for short-haul and long-haul applications.
Each transceiver is composed of a line interface unit (LIU), framer, and two additional HDLC controllers. The
transceivers are software compatible with the popular DS2155 and DS21455.
The LIU is composed of a transmit interface, receive interface, and a jitter attenuator. The transmit interface is
responsible for generating the necessary waveshapes for driving the network and providing the correct source
impedance depending on the type of media used. T1 waveform generation includes DSX-1 line build-outs as well
as CSU line build-outs of -7.5dB, -15dB, and -22.5dB. E1 waveform generation includes G.703 waveshapes for
both 75Ω coax and 120Ω twisted cables. The receive interface provides network termination and recovers clock
and data from the network. The receive sensitivity adjusts automatically to the incoming signal and can be
programmed for 0dB to 43dB or 0dB to 12dB for E1 applications and 0dB to 15dB or 0dB to 36dB for T1
applications. The jitter attenuator removes phase jitter from the transmitted or received signal. The crystal-less jitter
attenuator requires only a 2.048MHz MCLK for both E1 and T1 applications (with the option of using a 1.544MHz
MCLK in T1 applications) and can be placed in either transmit or receive data paths. An additional feature of the
LIU is a CMI coder/decoder for interfacing to optical networks.
On the transmit side, clock/data, and frame-sync signals are provided to the framer by the backplane interface
section. The framer inserts the appropriate synchronization framing patterns and alarm information, calculates and
inserts the CRC codes, and provides the B8ZS/HDB3 (zero code suppression) and AMI line coding. The receive-
side framer decodes AMI, B8ZS, and HDB3 line coding, synchronizes to the data stream, reports alarm
information, counts framing/coding/CRC errors, and provides clock/data and frame-sync signals to the backplane
interface section.
The transmit and receive paths of the integrated transceivers also have two HDLC controllers. The HDLC
controllers transmit and receive data via the framer block. The HDLC controllers can be assigned to any time slot,
group of time slots, portion of a time slot, or to FDL (T1) or Sa bits (E1). Each controller has 128-bit FIFOs, thus
reducing the amount of processor overhead required to manage the flow of data. In addition, built-in support for
reducing the processor time required handles SS7 applications.
The backplane interface of the integrated transceivers provides a method of sending and receiving data from the
integrated Ethernet Mapper over an interleaved 8.192MHz TDM (IBO) bus. The elastic stores are required for IBO
operation and they manage slip conditions.
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