DS33R41+ Maxim Integrated Products, DS33R41+ Datasheet - Page 14

• Manufacturer Part Number: DS33R41+
• Description: IC TXRX ETHERNET MAP 400-BGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS33R41+

• Number Of Drivers/receivers: 4/4
• Protocol: T1/E1/J1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.14 System Interface
2.15 Test and Diagnostics
2.16 Specifications Compliance
The DS33R41 meets relevant telecommunications specifications. The following table provides the specifications
and relevant sections that are applicable to the DS33R41.
Table 2-1. T1-Related Telecommunications Specifications
IEEE 802.3-2002 - CSMA/CD access method and physical layer specifications.
RFC1662 - PPP in HDLC-like Framing
RFC2615 - PPP over SONET/SDH
X.86 - Ethernet over LAPS
RMII - Industry Implementation Agreement for “Reduced MII Interface,” Sept 1997
ANSI - T1.403-1995, T1.231-1993, T1.408
AT&T: TR54016, TR62411
ITU: G.703, G.704, G.706, G.736, G.775, G.823, G.932, I.431, O.151, O.161
ETS: ETS 300 011, ETS 300 166, ETS 300 233, CTR4, CTR12
Japanese: JTG.703, JTI.431, JJ-20.11 (CMI coding only)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Dual two-frame, independent receive and transmit elastic stores
Supports T1 to E1 conversion
Ability to pass the T1 F-bit position through the elastic stores in the 2.048MHz backplane mode
Programmable output clocks for fractional T1, E1, H0, and H12 applications
Interleaving PCM bus operation with rates of 4.096MHz, 8.192MHz, and 16.384MHz
Hardware-signaling capability
Access to the data streams in between the framer/formatter and the elastic stores
User-selectable synthesized clock output
IEEE 1149.1 Support
Programmable on-chip BERT
Patterns include Pseudorandom QRSS, Daly, and user-defined repetitive patterns
Error insertion for a single bit or continuous
Insertion options include continuous and absolute number with selectable insertion rates
Total-bit and errored-bit counters
Payload Error Insertion
Errors can be inserted over the entire frame or selected channels
F-bit corruption for line testing
Loopbacks (remote, local, analog, and per-channel payload loopback)
o
o
o
o
o
o
Independent control and clocking
Controlled-slip capability with status
Minimum-delay mode supported
Receive-signaling reinsertion to a backplane, multiframe sync
Availability of signaling in a separate PCM data stream
Signaling freezing
14 of 335