DS33R41+ Maxim Integrated Products, DS33R41+ Datasheet - Page 30

• Manufacturer Part Number: DS33R41+
• Description: IC TXRX ETHERNET MAP 400-BGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS33R41+

• Number Of Drivers/receivers: 4/4
• Protocol: T1/E1/J1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SYSCLKI
BPCLK1
BPCLK2
JTCLK1
JTCLK2
JTRST1
JTRST2
MCLK1
MCLK2
JTDO1
JTMS1
JTDO2
NAME
JTDI1
JTDI2
DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers
G14
G13
Y14
K17
H14
PIN
L12
L13
L10
J17
G8
C7
K2
P9
L3
TYPE
Ipu
Ipu
Ipu
Ipu
Ipu
Ipu
Ipu
Oz
Oz
O
O
I
I
I
System Clock In. 100MHz System Clock input to the DS33R41, used for
internal operation. This clock is buffered and provided at SDCLKO for the
SDRAM interface. The DS33R41 also provides a divided version output
at the REF_CLKO pin. A clock supply with ±100ppm frequency accuracy
is suggested.
Backplane Clock, Transceiver 1. A user-selectable synthesized clock
output that is referenced to the clock that is output at the RCLK1 pin.
Backplane Clock, Transceiver 2. A user-selectable synthesized clock
output that is referenced to the clock that is output at the RCLK2 pin.
Master Clock for Transceiver 1 and Transceiver 2. A (50ppm) clock
source. This clock is used internally for both clock/data recovery and for
the jitter attenuator for both T1 and E1 modes. The clock rate can be
16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz. When using the
transceiver in T1-only operation a 1.544MHz (50ppm) clock source can
be used. MCLK1 and MCLK2 can be driven from a common clock.
Master Clock for Transceiver 3 and Transceiver 4. A (50ppm) clock
source. This clock is used internally for both clock/data recovery and for
the jitter attenuator for both T1 and E1 modes. The clock rate can be
16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz. When using the
transceiver in T1-only operation a 1.544MHz (50ppm) clock source can
be used. MCLK1 and MCLK2 can be driven from a common clock.
JTAG Clock for the Ethernet Mapper. This signal is used to shift data
into JTDI1 on the rising edge and out of JTDO1 on the falling edge.
JTAG Data In for the Ethernet Mapper. Test instructions and data are
clocked into this pin on the rising edge of JTCLK1. This pin has a 10kΩ
pullup resistor.
JTAG Reset for the Ethernet Mapper. JTRST1 is used to
asynchronously reset the test access port controller. After power up, a
rising edge on JTRST1 will reset the test port and cause the device I/O to
enter the JTAG DEVICE ID mode. Pulling JTRST1 low restores normal
device operation. JTRST1 is pulled HIGH internally via a 10kΩ resistor
operation. If boundary scan is not used, this pin should be held low.
JTAG Data Out for the Ethernet Mapper. Test instructions and data are
clocked out of this pin on the falling edge of JTCLK1. If not used, this pin
should be left unconnected.
JTAG Mode Select for the Ethernet Mapper. This pin is sampled on the
rising edge of JTCLK1 and is used to place the test access port into the
various defined IEEE 1149.1 states. This pin has a 10kΩ pullup resistor.
JTAG Clock 2 for the T1/E1/J1 Transceivers. This signal is used to shift
data into JTDI2 on the rising edge and out of JTDO2 on the falling edge
JTAG Data In 2 for the T1/E1/J1 Transceivers. Test instructions and
data are clocked into this pin on the rising edge of JTCLK2. This pin has a
10kΩ pullup resistor.
JTAG Reset 2 for the T1/E1/J1 Transceivers. JTRST2 is used to
asynchronously reset the test access port controller. After power-up,
JTRST2 must be toggled from low to high. This action will set the device
into the JTAG DEVICE ID mode. Normal device operation is restored by
pulling JTRST2 low. JTRST2 is pulled HIGH internally via a 10kΩ resistor
operation.
JTAG Data Out 2 for the T1/E1/J1 Transceivers. Test instructions and
data are clocked out of this pin on the falling edge of JTCLK2. If not used,
this pin should be left unconnected.
JTAG INTERFACES
SYSTEM CLOCKS
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FUNCTION