DS33R41+ Maxim Integrated Products, DS33R41+ Datasheet - Page 36

• Manufacturer Part Number: DS33R41+
• Description: IC TXRX ETHERNET MAP 400-BGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS33R41+

• Number Of Drivers/receivers: 4/4
• Protocol: T1/E1/J1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9 ETHERNET MAPPER
9.1 Ethernet Mapper Clocks
The DS33R41 clocks sources and functions are as follows:
The following table provides the different clocking options for the Ethernet interface.
Table 9-1. Clocking Options for the Ethernet Interface
RMIIMIIS
1 (RMII)
1 (RMII)
0 (MII)
0 (MII)
0 (MII)
Pin
•
•
•
•
•
•
Serial Transmit Data (TCLKE) and Serial Receive Data (RCLKI) clock inputs are used to transfer data from
the serial interface. These clocks can be continuous or gapped.
System Clock (SYSCLKI) input. Used for internal operation. This clock input cannot be a gapped clock. A
clock supply with ±100ppm frequency accuracy is suggested. A buffered version of this clock is provided
on the SDCLKO pin for the operation of the SDRAM. A divided and buffered version of this clock is
provided on REF_CLKO for the RMII/MII interface.
Packet Interface Reference clock (REF_CLK) input that can be 25MHz or 50MHz. This clock is used as
the timing reference for the RMII/MII interface.
The Transmit and Receive clocks for the MII Interface (TX_CLK and RX_CLK). In DTE mode, these are
input pins and accept clocks provided by an Ethernet PHY. In the DCE mode, these are output pins and
will output an internally generated clock to the Ethernet PHY. The output clocks are generated by internal
division of REF_CLK. In RMII mode, only the REF_CLK input is used.
REF_CLKO is an output clock that is generated by dividing the 100MHz System clock (SYSCLKI) by 2 or
4.
A Management Data Clock (MDC) output is derived from SYSCLKI and is used for information transfer
between the internal Ethernet MAC and external PHY. The MDC clock frequency is 1.67MHz.
100Mbps
100Mbps
10Mbps
10Mbps
10Mbps
Speed
DCE/
DCE
DCE
DTE
DTE
—
—
REF_CLKO
Output
25MHz
25MHz
25MHz
50MHz
50MHz
REF_CLK
±100ppm
±100ppm
±100ppm
±100ppm
±100ppm
25MHz
25MHz
25MHz
50MHz
50MHz
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Input
Not Applicable
Not Applicable
Input from
RX_CLK
(Output)
(Output)
2.5MHz
25MHz
PHY
Not Applicable
Not Applicable
Input from
TX_CLK
(Output)
(Output)
2.5MHz
25MHz
PHY
1.67MHz
1.67MHz
1.67MHz
1.67MHz
1.67MHz
Output
MDC