DS33R41+ Maxim Integrated Products, DS33R41+ Datasheet - Page 177

• Manufacturer Part Number: DS33R41+
• Description: IC TXRX ETHERNET MAP 400-BGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS33R41+

• Number Of Drivers/receivers: 4/4
• Protocol: T1/E1/J1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.6.2 MAC Registers
The control Registers related to the control of the individual MACs are shown in the following table. The device
keeps statistics for the packet traffic sent and received. The register address map is shown in the following table.
Note that the addresses listed are the indirect addresses that must be provided to
or SU.MACAWH/SU.MACAWL.
Register Name:
Register Description:
Register Address:
0000h:
Bit #
Name
Default
0001h:
Bit #
Name
Default
0002h:
Bit #
Name
Default
0003h:
Bit #
Name
Default
Bit 28: Heartbeat Disable (HDB). When set to 1, the heartbeat (SQE) function is disabled. This bit should be set
to 1 when operating in MII mode.
Bit 27: Port Select (PS). This bit should be equal to 0 for proper operation.
Bit 23: Disable Receive Own (DRO). When set to 1, the MAC disables the reception of frames while TX_EN is
asserted. When this bit equals zero, transmitted frames are also received by the MAC. This bit should be cleared
when operating in full-duplex mode.
Bit 21: Loopback Operating Mode (OMLO). When set to 1, data is looped from the transmit side, back to the
receive side, without being transmitted to the PHY.
Bit 20: Full-Duplex Mode Select (F). When set to 1, the MAC transmits and receives data simultaneously. When
in full-duplex mode, the heartbeat check is disabled and the heartbeat fail status should be ignored.
Bit 19: Promiscuous Mode (PM) When set to 1, the MAC is in Promiscuous Mode and forwards all frames. Note
that the default value is 1.
Bit 18: Pass All Multicast (PAM) When set to 1, the MAC forwards Multicast Frames.
Bit 12: Late Collision Control (LCC). When set to 1, enables retransmission of a collided packet even after the
collision period. When this bit is clear, retransmission of late collisions is disabled.
Bit 10: Disable Retry (DRTY). When set to 1, the MAC makes only a single attempt to transmit each frame. If a
collision occurs, the MAC ignores the current frame and proceeds to the next frame. When this bit equals 0, the
MAC will retry collided packets 16 times before signaling a retry error.
Reserved
Reserved
BOLMT1
DRO
31
23
15
07
0
0
0
0
BOLMT0
Reserved
Reserved
Reserved
06
30
22
14
0
0
0
0
SU.MACCR
MAC Control Register
0000h (indirect)
Reserved
Reserved
OML0
DC
05
29
21
13
0
0
0
0
Reserved
177 of 335
HDB
LCC
28
20
12
04
F
0
0
0
0
Reserved
PM
PS
TE
27
19
11
03
0
0
0
0
Reserved
DRTY
PAM
RE
26
18
10
02
0
0
0
0
SU.MACRADH/SU.MACRADL
Reserved
Reserved
Reserved
Reserved
25
17
09
01
0
0
0
0
Reserved
Reserved
Reserved
ASTP
00
24
16
08
0
0
0
0