DS33R41+ Maxim Integrated Products, DS33R41+ Datasheet - Page 171

• Manufacturer Part Number: DS33R41+
• Description: IC TXRX ETHERNET MAP 400-BGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS33R41+

• Number Of Drivers/receivers: 4/4
• Protocol: T1/E1/J1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Under Run (UR). When this bit is set to 1, the frame was aborted due to a data under run condition of the
transmit buffer.
Bit 6: Excessive Collisions (EC). When this bit is set to 1, a frame has been aborted after 16 successive
collisions while attempting to transmit the current frame. If the Disable Retry bit is set to 1, then Excessive
Collisions will be set to 1 after the first collision.
Bit 5: Late Collision (LC). When this bit is set to 1, a frame was aborted by collision after the 64 bit collision
window. Not valid if an under run has occurred.
Bit 4: Excessive Deferral (ED). When this bit is set to 1, a frame was aborted due to excessive deferral.
Bit 3: Loss Of Carrier (LOC). When this bit is set to 1, a frame was aborted due to loss of carrier for one or more
bit times. Valid only for non-collided frames. Valid only in half-duplex operation.
Bit 2: No Carrier (NOC). When this bit is set to 1, a frame was aborted because no carrier was found for
transmission.
Bit 1: Reserved.
Bit 0: Frame Abort (FABORT). When this bit is set to 1, the MAC has aborted a frame for one of the above
reasons. When this bit is clear, the previous frame has been transmitted successfully.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Packet Resend (PR). When this bit is set, the current packet must be retransmitted due to a collision.
Bit 6: Heartbeat Failure (HBF). When this bit is set, the device failed to detect a heart beat after transmission.
This bit is not valid if an under run has occurred.
Bits 5 to 2: Collision Count (CC3 to CC0). These four bits indicate the number of collisions that occurred prior to
successful transmission of the previous frame. Not valid if Excessive Collisions is set to 1.
Bit 1: Late Collision (LCO). When set to 1, the MAC observed a collision after the 64-byte collision window.
Bit 0: Deferred Frame (DEF). When set to 1, the current frame was deferred due to carrier assertion by another
node after being ready to transmit.
UR
PR
7
0
7
0
HBF
EC
6
0
6
0
SU.TFSL
Transmit Frame Status Low
152h
SU.TFSH
Transmit Frame Status High
153h
CC3
LC
5
0
5
0
171 of 335
CC2
ED
0
0
4
4
LOC
CC1
3
0
3
0
NOC
CC0
2
0
2
0
LCO
—-
1
0
1
0
FABORT
DEF
0
0
0
0