DS33R41+ Maxim Integrated Products, DS33R41+ Datasheet - Page 3

• Manufacturer Part Number: DS33R41+
• Description: IC TXRX ETHERNET MAP 400-BGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS33R41+

• Number Of Drivers/receivers: 4/4
• Protocol: T1/E1/J1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10
9.12 E
9.13 E
9.14 T
9.15 R
9.16 X.86 E
9.17 C
10.1 T1/E1/J1 T
10.2 P
10.3 T1/E1/J1 T
10.4 T1 F
10.5 E1 F
10.6 L
10.7 E
10.8 DS0 M
10.9 S
10.10 P
10.11 C
10.12 E
10.13 G.706 I
10.14 T1 B
10.15 R
10.16 A
10.17 A
9.11.1 Full Duplex Flow Control.......................................................................................................................51
9.11.2 Half Duplex Flow Control ......................................................................................................................53
9.11.3 Host-Managed Flow Control .................................................................................................................53
9.12.1 DTE and DCE Mode .............................................................................................................................56
9.13.1 MII Mode ...............................................................................................................................................59
9.13.2 RMII Mode.............................................................................................................................................59
9.13.3 PHY MII Management Block and MDIO Interface ................................................................................60
INTEGRATED T1/E1/J1 TRANSCEIVERS...................................................................................... 68
10.4.1 T1 Transmit Transparency....................................................................................................................70
10.4.2 AIS-CI and RAI-CI Generation and Detection ......................................................................................70
10.4.3 T1 Receive-Side Digital-Milliwatt Code Generation..............................................................................71
10.5.1 Automatic Alarm Generation.................................................................................................................73
10.6.1 Per-Channel Payload Loopback ...........................................................................................................75
10.7.1 Line-Code Violation Counter (TR.LCVCR) ...........................................................................................76
10.7.2 Path Code Violation Count Register (TR.PCVCR) ...............................................................................77
10.7.3 Frames Out-of-Sync Count Register (TR.FOSCR) ..............................................................................78
10.7.4 E-Bit Counter (TR.EBCR) .....................................................................................................................78
10.9.1 Processor-Based Receive Signaling ....................................................................................................80
10.9.2 Hardware-Based Receive Signaling .....................................................................................................81
10.9.3 Processor-Based Transmit Signaling ...................................................................................................82
10.9.4 Hardware-Based Transmit Signaling ....................................................................................................83
10.10.1 Idle-Code Programming Examples .......................................................................................................85
10.12.1 Receive Side .........................................................................................................................................86
10.12.2 Transmit Side ........................................................................................................................................87
10.12.3 Elastic Stores Initialization ....................................................................................................................87
10.14.1 Transmit BOC .......................................................................................................................................89
10.16.1 Method 1: Internal Register Scheme Based on Double-Frame............................................................90
10.16.2 Method 2: Internal Register Scheme Based on CRC4 Multiframe .......................................................90
10.17.1 HDLC Configuration..............................................................................................................................91
10.17.2 FIFO Control .........................................................................................................................................93
10.17.3 HDLC Mapping......................................................................................................................................94
10.17.4 FIFO Information ...................................................................................................................................95
OOPBACK
RANSMIT
THERNET
THERNET
ER
RROR
IGNALING
ER
LASTIC
DDITIONAL
DDITIONAL
ECEIVE
OMMITTED
HANNEL
ECEIVE
-C
-C
RAMER
RAMER
IT
HANNEL
HANNEL
-O
NCODING AND
ONITORING
NTERMEDIATE
C
S
P
RIENTED
BOC .............................................................................................................................. 89
OUNTERS
B
TORES
P
ACKET
I
MAC ........................................................................................................................... 57
O
C
RANSCEIVER
RANSCEIVER
LOCKING
/F
NTERFACE
/F
ACKET
(S
HDLC C
I
ONFIGURATIONS
PERATION
NFORMATION
ORMATTER
ORMATTER
A
O
I
DLE
)
PERATION
AND
O
P
C
F
........................................................................................................................ 76
P
ROCESSOR
PERATION
C
ODE
UNCTION
ROCESSOR
R
ONTROLLERS IN
D
ODE
CRC-4 U
I
EGISTERS
NTERNATIONAL
P
ECODING
................................................................................................................. 80
ORT
C
I
(BOC) C
NTERRUPTS
C
C
LOCKS
G
R
............................................................................................................ 69
ONTROL AND
ONTROL AND
ENERATION
ATE
......................................................................................................... 54
........................................................................................................ 74
........................................................................................................ 79
........................................................................................................ 86
...................................................................................................... 62
PDATING
.................................................................................................... 61
.................................................................................................... 64
C
................................................................................................... 86
.................................................................................................. 68
ONTROLLER
ONTROLLER
T1/E1/J1 T
............................................................................................ 69
(S
........................................................................................ 84
S
S
I
(E1 M
) B
TATUS
TATUS
3 of 335
IT
............................................................................... 89
.............................................................................. 67
O
ODE
PERATION
........................................................................... 70
........................................................................... 72
RANSCEIVER
O
NLY
)............................................................ 88
(E1 O
....................................................... 91
NLY
)........................................... 90