EP2SGX90EF1152C5ES Altera, EP2SGX90EF1152C5ES Datasheet - Page 24
EP2SGX90EF1152C5ES
Manufacturer Part Number
EP2SGX90EF1152C5ES
Description
IC STRATIX II GX 90K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX90EF1152C5ES
Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520448
Number Of I /o
558
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
1152-FBGA
For Use With
544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1765
Available stocks
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Manufacturer
Quantity
Price
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Transceivers
2–16
Stratix II GX Device Handbook, Volume 1
Figure 2–13. Programmable Receiver Termination
If a design uses external termination, the receiver must be externally
terminated and biased to 0.85 V or 1.2 V.
of an external termination and biasing circuit.
Figure 2–14. External Termination and Biasing Circuit
Programmable Equalizer
The Stratix II GX receivers provide a programmable receive equalization
feature to compensate the effects of channel attenuation for high-speed
signaling. PCB traces carrying these high-speed signals have low-pass
filter characteristics. The impedance mismatch boundaries can also cause
signal degradation. The equalization in the receiver diminishes the lossy
attenuation effects of the PCB at high frequencies.
50/60/75- Ω
Termination
Resistance
Transmission
Line
50, 60, or 75 Ω
50, 60, or 75 Ω
V
Receiver External Termination
and Biasing
DD
× {R2/(R1 + R 2)} = 0.85/1.2 V
Receiver External Termination
R1/R2 = 1K
V
C1
and Biasing
DD
V
CM
Figure 2–14
R2
R1
Stratix II GX Device
shows an example
Differential
Altera Corporation
Buffer
RXIN
RXIP
Input
Receiver
October 2007
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