EP2SGX90EF1152C5ES Altera, EP2SGX90EF1152C5ES Datasheet - Page 11
EP2SGX90EF1152C5ES
Manufacturer Part Number
EP2SGX90EF1152C5ES
Description
IC STRATIX II GX 90K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX90EF1152C5ES
Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520448
Number Of I /o
558
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
1152-FBGA
For Use With
544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1765
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Altera Corporation
October 2007
Figure 2–2. Elements of the Transceiver Block
Each Stratix II GX transceiver channel consists of a transmitter and
receiver. The transceivers are grouped in four and share PLL resources.
Each transmitter has access to one of two PLLs. The transmitter contains
the following:
■
■
■
■
■
The receiver contains the following:
■
■
■
■
■
■
■
■
■
■
■
■
Designers can preset Stratix II GX transceiver functions using the
Quartus
differential output voltage (V
Stratix II GX transceiver channel supports various loopback modes and is
Transmitter phase compensation first-in first-out (FIFO) buffer
Byte serializer (optional)
8B/10B encoder (optional)
Serializer (parallel-to-serial converter)
Transmitter differential output buffer
Receiver differential input buffer
Receiver lock detector and run length checker
Clock recovery unit (CRU)
Deserializer
Pattern detector
Word aligner
Lane deskew
Rate matcher (optional)
8B/10B decoder (optional)
Byte deserializer (optional)
Byte ordering
Receiver phase compensation FIFO buffer
®
II software. In addition, pre-emphasis, equalization, and
Stratix II GX
Logic Array
Transceiver Block
(PLLs, State Machines,
OD
Supporting Blocks
Programming)
) are dynamically programmable. Each
Channel 1
Channel 0
Channel 2
Channel 3
Stratix II GX Device Handbook, Volume 1
Stratix II GX Architecture
RX1
TX1
RX0
TX0
REFCLK_1
REFCLK_0
RX2
TX2
RX3
TX3
2–3
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