EP2SGX90EF1152C5ES Altera, EP2SGX90EF1152C5ES Datasheet - Page 117
EP2SGX90EF1152C5ES
Manufacturer Part Number
EP2SGX90EF1152C5ES
Description
IC STRATIX II GX 90K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX90EF1152C5ES
Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520448
Number Of I /o
558
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
1152-FBGA
For Use With
544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1765
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Figure 2–74. Stratix II GX Enhanced PLL
Notes to
(1)
(2)
(3)
(4)
Altera Corporation
October 2007
Global or
Regional
Clock
INCLK[3..0]
Each clock source can come from any of the four clock pins that are physically located on the same side of the device
as the PLL.
If the feedback input is used, you will lose one (or two, if FBIN is differential) external clock output pin.
Each enhanced PLL has three differential external clock outputs or six single-ended external clock outputs.
The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or
regional clock, or through a clock control block provided the clock control block is fed by an output from another
PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL.
Figure
4
Shaded Portions of the
PLL are Reconfigurable
2–74:
FBIN
Switchover
Circuitry
Clock
(2)
Enhanced PLLs
Stratix II GX devices contain up to four enhanced PLLs with advanced
clock management features. These features include support for external
clock feedback mode, spread-spectrum clocking, and counter cascading.
Figure 2–74
Fast PLLs
Stratix II GX devices contain up to four fast PLLs with high-speed serial
interfacing ability. The fast PLLs offer high-speed outputs to manage the
high-speed differential I/O interfaces.
the fast PLL.
/n
Phase Frequency
Detector
PFD
shows a diagram of the enhanced PLL.
Charge
Pump
Note (1)
Lock Detect
& Filter
Spectrum
/m
Spread
Loop
Filter
VCO Phase Selection
Affecting All Outputs
VCO Phase Selection
Selectable at Each
PLL Output Port
VCO
Stratix II GX Device Handbook, Volume 1
8
Figure 2–75
Post-Scale
Counters
/c0
/c1
/c2
/c3
/c4
/c5
From Adjacent PLL
6
Stratix II GX Architecture
shows a diagram of
4
8
6
Global
Clocks
Regional
Clocks
I/O Buffers (3)
to I/O or general
routing
2–109
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