EP2SGX90EF1152C5ES Altera, EP2SGX90EF1152C5ES Datasheet - Page 122
EP2SGX90EF1152C5ES
Manufacturer Part Number
EP2SGX90EF1152C5ES
Description
IC STRATIX II GX 90K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX90EF1152C5ES
Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520448
Number Of I /o
558
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
1152-FBGA
For Use With
544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1765
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I/O Structure
Figure 2–78. Column I/O Block Connection to the Interconnect
Note to
(1)
2–114
Stratix II GX Device Handbook, Volume 1
The 32 data and control signals consist of eight data out lines: four lines each for DDR applications
io_dataouta[3..0] and io_dataoutb[3..0], four output enables io_oe[3..0], four input clock enables
io_ce_in[3..0], four output clock enables io_ce_out[3..0], four clocks io_clk[3..0], four asynchronous
clear and preset signals io_aclr/apreset[3..0], and four synchronous clear and preset signals
io_sclr/spreset[3..0]
Figure
Local Interconnect
from Logic Array (1)
Interconnects
R4 & R24
Control Signals
2–78:
I/O Block
32 Data &
Interconnect
LAB
LAB Local
Figure 2–78
.
shows how a column I/O block connects to the logic array.
Vertical I/O Block
Interconnects
C4 & C16
32
LAB
IO_dataina[3..0]
IO_datainb[3..0]
LAB
Vertical I/O
Block Contains
up to Four IOEs
io_clk[7..0]
Altera Corporation
October 2007
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