GCIXP1250BA 837411 Intel, GCIXP1250BA 837411 Datasheet - Page 6

• Manufacturer Part Number: GCIXP1250BA 837411
• Manufacturer: Intel

Specifications of GCIXP1250BA 837411

• Lead Free Status / Rohs Status: Supplier Unconfirmed

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IXP1250 Network Processor
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32-Bit Unidirectional IX Bus Timing - Consecutive Receives, EOP on
14th Data Return with Status ............................................................................ 104
32-Bit Unidirectional IX Bus Timing - Consecutive Receives, EOP on 1st
Through 13th Data Return with Status (13th Data Return Shown) ................... 105
32-Bit Unidirectional IX Bus Timing - Consecutive Receives, EOP, 64-Bit
Status ................................................................................................................ 106
32-Bit Unidirectional IX Bus Timing - Consecutive Receives, Two Element
Transfers with 32-Bit Status .............................................................................. 107
32-Bit Unidirectional IX Bus Timing - Consecutive Transmits, EOP ................. 108
32-Bit Unidirectional IX Bus Timing - Consecutive Transmits with Prepend,
EOP................................................................................................................... 109
64-Bit Bidirectional IX Bus Timing - Consecutive FastPort Receives, Same
Port, EOP, No Status, FP_READY_WAIT=0 .................................................... 110
64-Bit Bidirectional IX Bus Timing - Consecutive FastPort Receives, Same
Port, EOP, No Status, FP_READY_WAIT=5 .................................................... 111
64-Bit Bidirectional IX Bus Timing - Consecutive FastPort Receives, Same
Port, EOP, with Status, FP_READY_WAIT=0 .................................................. 112
64-Bit Bidirectional IX Bus Timing - Consecutive FastPort Receives, Same
Port, EOP, No Status, FP_READY_WAIT=5 .................................................... 113
64-Bit Bidirectional IX Bus Timing - Consecutive FastPort Receives, Same
Port, EOP, No Status, FP_READY_WAIT=0, Cancelled Request.................... 114
64-Bit Bidirectional IX Bus Timing - Consecutive FastPort Receives, Same
Port, No EOP, FP_READY_WAIT=Don’t Care ................................................. 115
64-Bit Bidirectional IX Bus Timing - Consecutive FastPort Receives, Different
Ports, EOP, No Status, FP_READY_WAIT=0 .................................................. 116
64-Bit Bidirectional IX Bus Timing - Consecutive FastPort Receives, Different
Ports, EOP, No Status, FP_READY_WAIT=0, Cancelled Request .................. 117
Consecutive Fetch Ready Flags, 1-2 MAC Mode (with No External Registered
Decoder) - RDYBUS_TEMPLATE_CTL[10]=1 ................................................. 118
Consecutive Fetch Ready Flags, 3+ MAC Mode (with External Decoder) -
RDYBUS_TEMPLATE_CTL[10]=0 ................................................................... 118
Fetch Ready Flags, Get/Send Commands, 3+ MAC Mode (with External
Registered Decoder) - RDYBUS_TEMPLATE_CTL[10]=0 ............................... 119
Ready Bus Control Timing, Fetch Ready Flags - Flow Control - Fetch Ready
Flags, 1-2 MAC Mode (with No External Registered Decoder) -
RDYBUS_TEMPLATE_CTL[10]=1 ................................................................... 119
Ready Bus Control Timing, Fetch Ready Flags - Flow Control - Fetch Ready
Flags, 3+ MAC Mode (with External Registered Decoder) -
RDYBUS_TEMPLATE_CTL[10]=0 ................................................................... 120
IX Bus Ownership Passing................................................................................ 121
SRAM SCLK Signal AC Parameter Measurements.......................................... 121
SRAM Bus Signal Timing.................................................................................. 122
Pipelined SRAM Read Burst of Eight Longwords ............................................. 124
Pipelined SRAM Write Burst of Eight Longwords ............................................. 125
Pipelined SRAM Read Burst of Four From Bank 0 Followed by Write Burst
of Four From Bank 8 ......................................................................................... 126
Pipelined SRAM Longword Write Followed by 2 Longword Burst Read
Followed by 4 Longword Burst Write ................................................................ 127
Flowthrough SRAM Read Burst of Eight Longwords ........................................ 128
BootROM Read................................................................................................. 129
BootROM Write ................................................................................................. 130
Pipelined SRAM Two Longword Burst Read Followed by BootROM Write ...... 131
SRAM SlowPort Read....................................................................................... 132
Datasheet