GCIXP1250BA 837411 Intel, GCIXP1250BA 837411 Datasheet - Page 22

• Manufacturer Part Number: GCIXP1250BA 837411
• Manufacturer: Intel

Specifications of GCIXP1250BA 837411

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Intel
2.6
2.6.1
22
®
IXP1250 Network Processor
PCI Unit
The PCI Unit provides an industry standard 32-bit PCI Bus to interface to PCI peripheral devices
such as host processors and MAC devices. The PCI Unit supports operating speeds from DC up to
66 MHz, and supports PCI Local Bus Specification, Revision 2.2. This unit contains:
Refer to the IXP1200 Network Processor Family Hardware Reference Manual for details on PCI
Bus behavior for Target (Slave) and Initiator (Master) modes, configuration and register
definitions.
The PCI interface is specified to operate from DC up to 66 MHz. Above 33 MHz operation, two
PCI devices are supported only, the IXP1250 and a second PCI device. To increase the number of
PCI devices supported or to add connectors to the bus at the higher PCI Bus speeds, a PCI-to-PCI
bridge device, such the Intel 21150, 21152, or 21153 is required.
Both PCI Initiator and Target cycles are supported. As a target device, the IXP1250 responds as a
Medium Speed device asserting DEVSEL_L two PCI_CLK cycles after FRAME_L is asserted.
PCI Arbitration and Central Function Support
The IXP1250 contains an optional arbiter to support up to three PCI Bus masters. This includes the
IXP1250 plus two external PCI Bus master devices. The external masters are supported by two
request signals, REQ_L[1:0], and two grant signals GNT_L[1:0].
The IXP1250 can also provide PCI Central Function support. In this configuration, the IXP1250:
Two configuration pins, PCI_CFN[1:0], are sampled at the rising edge of RESET_IN_L to
determine the PCI configuration (see
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Arbitration logic to support up to three PCI Bus masters,
PCI Intelligent I/O (I
Two DMA channels, and
Four 24-bit timers.
Drives the PCI Reset signal, PCI_RST_L, as an output,
Monitors the PCI System Error input signal, SERR_L, and
Provides Bus Parking where the IXP1250 is the default PCI Bus master, and it drives valid
logic levels on the PCI A/D, C/BE, and PAR pins during reset and idle PCI Bus conditions.
— The sram microinstruction defines the number of 32-bit accesses to make, up to 8
— Only bit and longword accesses are supported.
— Bit write accesses result in Read-Modify-Write cycles.
— Unlike the StrongARM* core, the Microengine microinstruction allows you to perform
longwords with one Microengine command.
bit operations within the instruction (Push, Pop, Bit Test and Set, CAM operations,
Lock/Unlock, etc.).
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Datasheet