GCIXP1250BA 837411 Intel, GCIXP1250BA 837411 Datasheet - Page 39

• Manufacturer Part Number: GCIXP1250BA 837411
• Manufacturer: Intel

Specifications of GCIXP1250BA 837411

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Datasheet
Table 18. PCI Interface Pins (Continued)
STOP_L
DEVSEL_L
IDSEL
PERR_L
SERR_L
PCI_IRQ_L
PCI_RST_L
PCI_CLK
Signal Names
PCI Interface
C13
B13
C17
D13
E13
B21
E20
D20
Number
Pin
I2/O2/
STS
I2/O2/
STS
I2
I2/O2/
STS
I2/O2/
OD
I2/O2/
OD
I2/O2/
TS
I2
Type
1
1
1
1
1
1
1
1
Total
Stop. Indicates that the target is requesting the master to
stop the current transaction. The IXP1250 drives as target
and receives as master.
Device Select. Indicates that the target has decoded its
address as the target of the current access. The IXP1250
drives as target and receives as initiator.
Initialization Device Select. Used as Chip Select during PCI
Configuration Space read and write transactions.
Parity error. Used to report data parity errors. The IXP1250
asserts this when it receives bad data parity as target of a
write or master of a read.
System Error.
As an input, it can cause an interrupt to the StrongARM* core
if the IXP1250 is selected for PCI Central Function and
arbitration support (PCI_CFN[1:0]=11).
As an output it can be asserted by the IXP1250 by writing the
SERR bit in the PCI control register, or in response to a PCI
address parity error when not providing PCI Central Function
and arbitration support (PCI_CFN[1:0]=00).
PCI Interrupt Request.
As output, used to interrupt the PCI Host Processor. It is
asserted when there is a doorbell set or there are messages
on the I
INTA_L on the PCI Bus.
As Input, It is asserted when there is a doorbell set or there
are messages on the I 2 O outbound post list.
PCI Reset.
PCI Clock input. Reference for PCI signals and internal
operations. PCI clock is typically 33 to 66 MHz.
• When providing PCI Central Function and arbitration
• When not providing PCI Central Function and arbitration
support (PCI_CFN[1:0]=11), PCI _RST_L is an output
controlled by the StrongARM* core. Used to reset the
PCI Bus.
(PCI_CFN[1:0]=00), PCI_RST_L is an input, and when
asserted resets the IXP1250 StrongARM* core, all
registers, all transaction queues, and all PCI related
state.
2
O outbound post list. This is usually connected to
Intel
Pin Descriptions
®
IXP1250 Network Processor
39