GCIXP1250BA 837411 Intel, GCIXP1250BA 837411 Datasheet - Page 17

• Manufacturer Part Number: GCIXP1250BA 837411
• Manufacturer: Intel

Specifications of GCIXP1250BA 837411

• Lead Free Status / Rohs Status: Supplier Unconfirmed

2.5.3
2.5.4
Datasheet
Table 5. SDRAM CRC Types
SDRAM Cyclic Redundancy Checking (CRC)
SDRAM Cyclic Redundancy Checking (CRC) is used to protect blocks of data called Frames.
Using this technique, the transmitter appends an extra n-bit sequence (called a Frame Check
Sequence or FCS) to every frame. The FCS holds redundant information about the frame that helps
the transmitter detect errors in the frame.
The CRC is one of the most used techniques for error detection in data communications. The
technique combines three advantages:
All CRC processing and checking is performed in software (microcode) and is only accessible
from microcode instructions.
The CRC types supported are described in
SDRAM Error Correction Code (ECC)
SDRAM Error Correction Code (ECC) allows data that is being read or transmitted to the SDRAM
to be checked for errors and, when necessary, corrected “on the fly.” It differs from standard
parity-checking because errors are not only detected but also corrected.
When a unit of data (or "word") is stored in SDRAM, a code that describes the bit sequence in the
word is calculated and stored along with that unit of data. For each 64-bit word, an extra 8 bits are
needed to store this code.
When the unit of data is requested for reading, a code for the stored and about-to-be-read word is
again calculated using the original algorithm. The newly generated code is compared with the code
generated when the word was stored.
CRC-32
CRC-16
CRC-10
•
•
•
•
CRC Type
Accesses from the Microengines.
Extreme error detection capabilities
Minimal overhead
Ease of implementation
— Read accesses using the Prefetch Memory address space allow the SDRAM Unit to
— The sdram microinstruction defines the number of 64-bit accesses to make, with up to 16
— Only quadword accesses are supported. Less than 8 bytes can be written when using the
prefetch quadword data to be supplied to the AMBA Bus using 32-bit burst cycles.
quadwords with one instruction.
byte mask within an instruction, but result in Read-Modify-Write cycles.
X
+X
X
x
10
32
16
7
+x
+X
+X
+X
9
26
12
5
+x
+X
+X
+X
5
4
+x
23
5
+X
+1
+X
4
+x+1
2
+X+1
Polynomial
22
+X
16
Table
+X
12
+X
5.
11
+X
10
Intel
+X
8
®
IXP1250 Network Processor
ATM AAL5
Ethernet
HDLC
Frame Relay
ATM OAM
Application
MSB first
LSB first
LSB first
LSB first
MSB first,
LW (or LW +1)
Bit Order
17