GCIXP1250BA 837411 Intel, GCIXP1250BA 837411 Datasheet - Page 139

• Manufacturer Part Number: GCIXP1250BA 837411
• Manufacturer: Intel

Specifications of GCIXP1250BA 837411

• Lead Free Status / Rohs Status: Supplier Unconfirmed

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Intel
IXP1250 Network Processor
SDRAMs timing values would appear consistent. tRC is used only to specify the number of cycles
between Refresh cycles during initialization of the SDRAM parts. It is possible to eliminate it
altogether, and simply have this time be the sum of tRP and tRASmin, as discussed above. The
IXP1200 Network Processor Family Micrcode Programmer’s Reference Manual refers to this as
the tRC Bank Cycle Time. Also referred to as “ACTIVE to ACTIVE command period” in SDRAM
datasheets.
tDPL
tDPL is the number of cycles after the final data write that a precharge may occur. tDPL = 1
indicates that a precharge may occur on the next cycle. The IXP1200 Network Processor Family
Micrcode Programmer’s Reference Manual refers to this as the tDPL Data In to Precharge Time.
Also referred to as “Data-in to PRECHARGE command time” in SDRAM datasheets.
tDQZ
tDQZ indicates the number of cycles of latency after DQM is seen that the SDRAMs will go into a
high-impedance state. For tDQZ = 2, DQM get sampled on the first edge, the SDRAMs get off the
bus on the next edge, and the bus may be driven on the third edge. The IXP1200 Network
Processor Family Micrcode Programmer’s Reference Manual refers to this as the tDQZ DQM Data
Out Disable Latency. Also referred to as “DQM to data high-impedance during READs” in
SDRAM datasheets.
tRWT
Note that for most designs, there may be a requirement to add one or more dead cycles after the
SDRAMs get off the bus to avoid possible bus contention on the DQM bus. This will be a function
of the design itself (i.e., component placement, bus loading, the SDRAMs used and tHZ, the time
that it takes for the SDRAM to go to a high-Z state) and the frequency at which the SDRAM
interface is running. If extra dead cycles are necessary on a write following read bus turnaround,
the tRWT should be programmed to a non-zero value. If tRWT is one, then one dead cycle will be
added following the completion of a read prior to a write access taking place. The IXP1200
Network Processor Family Micrcode Programmer’s Reference Manual refers to this as the tRWT
Read/write Turnaround Time. Not explicitly specified in SDRAM data sheets, but is a function of
memory system design, loading. Most PC100 type SDRAM devices allow a zero-delay read-write
turnaround. However, tHZmax for PC100 devices is 5.4ns (CASL=2) or 7 ns (CASL=3) and tON
for the IXP1250 is 1 ns, so a 1 clock tRWT would be required to avoid bus contention.
Datasheet
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