GCIXP1250BA 837411 Intel, GCIXP1250BA 837411 Datasheet - Page 42

• Manufacturer Part Number: GCIXP1250BA 837411
• Manufacturer: Intel

Specifications of GCIXP1250BA 837411

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Intel
3.3.9
3.3.10
42
Table 20. IEEE 1149.1 Interface Pins
Table 21. Miscellaneous Test Pins
®
IXP1250 Network Processor
IEEE 1149.1 Interface Pins
Miscellaneous Test Pins
TCK
TMS
TDI
TDO
TRST_L
Totals:
SCAN_EN
TCK_BYP
TSTCLK
Totals:
Support Signal
Interface Pin
IEEE 1149.1
Processor
Names
Name
C22
B22
C21
D21
D22
D7
C7
B7
Number
Number
Pin
Pin
I1
I1
I1
O1
I1
I1
I1
I1
Type
Type
1
1
1
1
1
5
1
1
1
3
Total
Total
Test Interface reference clock. This clock times all the
transfers on the IEEE 1149.1 test interface.
Test Interface mode select. Causes state transitions on the
test access port (TAP) controller.
Test Interface data input. The serial input through which
IEEE 1149.1 instructions and test data enter the IEEE
1149.1 interface.
Test Interface data output. The serial output through which
test instruction and data from the test logic leave the
IXP1250.
Test Interface RESET. When asserted low, the TAP
controller is asynchronously forced to enter a reset state,
and disables the IEEE 1149.1 port. This pin must be driven
or held low to achieve normal device operation.
Used for Intel test purposes only. Enables internal scan
chains for chip testing. This pin should be connected to
VSS through a pulldown resistor.
Used for Intel test purposes only. When high, bypasses
PLL for Test/debug. Must be low for normal system
operation.
Used for Intel test purposes only. Used as clock input
when bypassing the internal PLL clock generator. For
Normal operation, this pin should not be allowed to float.
It should be pulled up or pulled down through the proper
value resistor.
Pin Descriptions
Pin Description
Datasheet