GCIXP1250BA 837411 Intel, GCIXP1250BA 837411 Datasheet - Page 138

• Manufacturer Part Number: GCIXP1250BA 837411
• Manufacturer: Intel

Specifications of GCIXP1250BA 837411

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Intel
4.3.9.3
138
Table 52. Signal Delay Deratings for T
®
IXP1250 Network Processor
SDRAM Signal Protocol
This section describes the SDRAM timing parameters referenced in the SDRAM timing diagrams
that follow. This nomenclature is consistent with most JEDEC standard SDRAM devices.
tRP
tRP is the minimum number of cycles after a precharge cycle that a bank may be opened (or
"RASd"). The IXP1200 Network Processor Family Micrcode Programmer’s Reference Manual
refers to this as the tRP Precharge Time. Also referred to as “PRECHARGE command period” in
SDRAM datasheets.
tRASmin
tRASmin is the minimum number of cycles that a bank must be open before it can be closed using
a precharge command. The maximum time that a bank may be open, tRASmax, is not checked,
because the IXP1250 SDRAM Controller methodology is to close all banks after the usage is
complete. The IXP1200 Network Processor Family Micrcode Programmer’s Reference Manual
refers to this as the tRASmin Active Command Period. Also referred to as “ACTIVE to
PRECHARGE command period” in SDRAM datasheets.
tRCD
tRCD is the number of cycles between the bank opening (or "RAS") and any read or write
command (or "CAS"). The IXP1200 Network Processor Family Micrcode Programmer’s
Reference Manual refers to this as the tRCD RAS to CAS Delay. Also referred to as “ACTIVE to
READ or WRITE delay” in SDRAM datasheets.
tRRD
tRRD is the number of cycles between successive bank openings, or RAS cycles. The IXP1200
Network Processor Family Micrcode Programmer’s Reference Manual refers to this as the tRRD
Bank to Bank Delay Time. Also referred to as “ACTIVE bank A to ACTIVE bank B command” in
SDRAM datasheets.
tRC
tRC is the SDRAM bank cycle time, indicating that the minimum time that a command may be
active. For most cases, this is the sum of tRP and tRASmin, although there are some SDRAM data
sheets where the absolute time for tRC (in ns) is not equal to the sum (in ns) of tRP and tRASmin.
In these cases, typically when rounding up to an even number of clock cycles, they are equivalent.
Since the SDRAM Controller CSRs are programmed with a number of clock cycles, these
SDCLK
DQM
WE_L
RAS_L
CAS_L
MADR[14:0]
MDATA[63:0]
MDATA_ECC[7:0]
Signal
0.053
0.065
0.065
0.065
0.065
0.065
0.095
0.095
83 MHz
Maximum Derating (ns/pF)
val
(IX Bus Speed)
and T
—
0.06
0.06
0.06
0.06
0.06
0.09
0.09
100 MHz
ctl
—
0.031
0.031
0.031
0.031
0.031
0.035
0.035
116 MHz
0.025
0.03
0.03
0.03
0.03
0.03
0.03
0.03
83 MHz
Minimum Derating (ns/pF)
(IX Bus Speed)
—
0.025
0.025
0.025
0.025
0.025
0.025
0.025
100 MHz
Datasheet
—
0.015
0.015
0.015
0.015
0.015
0.015
0.015
116 MHz