IDT82V3255TFG IDT, Integrated Device Technology Inc, IDT82V3255TFG Datasheet - Page 86

• Manufacturer Part Number: IDT82V3255TFG
• Description: IC PLL WAN SMC STRATUM 3 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3255TFG

• Input: CMOS, LVDS, PECL
• Output: CMOS, LVDS, PECL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3255TFG

PRIORITY_TABLE2_STS - Priority Status 2 *
T0_INPUT_SEL_CNFG - T0 Selected Input Clock Configuration
Programming Information
IDT82V3255
Address: 4FH
Type: Read
Default Value: 00000000
Address: 50H
Type: Read / Write
Default Value: XXXX0000
ST_PRIORITY_
THIRD_HIGHE
VALIDATED3
7 - 4
3 - 0
7 - 4
3 - 0
Bit
Bit
7
7
-
T0_INPUT_SEL[3:0]
SECOND_HIGHEST_PRIORITY_VALIDATED[3:0]
THIRD_HIGHEST_PRIORITY_VALIDATED[3:0]
ST_PRIORITY_
THIRD_HIGHE
VALIDATED2
Name
-
6
-
6
Reserved.
This bit determines T0 input clock selection. It is valid only when the EXT_SW bit (b4, 0BH) is ‘0’.
0000: Automatic selection. (default)
0001, 0010: Reserved.
0011: Forced selection - IN1_CMOS is selected.
0100: Forced selection - IN2_CMOS is selected.
0101: Forced selection - IN1_DIFF is selected.
0110: Forced selection - IN2_DIFF is selected.
0111, 1000: Reserved.
1001: Forced selection - IN3_CMOS is selected.
1010 ~ 1111: Reserved.
Name
ST_PRIORITY_
THIRD_HIGHE
VALIDATED1
5
-
5
ST_PRIORITY_
THIRD_HIGHE
VALIDATED0
4
-
These bits indicate a qualified input clock with the third highest priority.
0000: No input clock is qualified. (default)
0001, 0010: Reserved.
0011: IN1_CMOS.
0100: IN2_CMOS.
0101: IN1_DIFF.
0110: IN2_DIFF.
0111, 1000: Reserved.
1001: IN3_CMOS.
1010 ~ 1111: Reserved.
These bits indicate a qualified input clock with the second highest priority.
0000: No input clock is qualified. (default)
0001, 0010: Reserved.
0011: IN1_CMOS.
0100: IN2_CMOS.
0101: IN1_DIFF.
0110: IN2_DIFF.
0111, 1000: Reserved.
1001: IN3_CMOS.
1010 ~ 1111: Reserved.
4
T0_INPUT_SEL3
86
SECOND_HIGH
EST_PRIORITY
_VALIDATED3
3
3
Description
T0_INPUT_SEL2
SECOND_HIGH
EST_PRIORITY
_VALIDATED2
2
2
Description
T0_INPUT_SEL1
SECOND_HIGH
EST_PRIORITY
_VALIDATED1
1
1
December 3, 2008
T0_INPUT_SEL0
SECOND_HIGH
EST_PRIORITY
_VALIDATED0
0
0
WAN PLL