IDT82V3255TFG IDT, Integrated Device Technology Inc, IDT82V3255TFG Datasheet - Page 37

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IDT82V3255TFG

Manufacturer Part Number
IDT82V3255TFG
Description
IC PLL WAN SMC STRATUM 3 64-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Type
PLL Clock Generatorr
Datasheet

Specifications of IDT82V3255TFG

Input
CMOS, LVDS, PECL
Output
CMOS, LVDS, PECL
Frequency - Max
622.08MHz
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Frequency-max
622.08MHz
Function
Wan PLL
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
TQFP
Pin Count
64
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
82V3255TFG

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Table 26: Outputs on OUT1 & OUT2 if Derived from T0/T4 APLL
Functional Description
IDT82V3255
OUTn_DIVIDER[3:0]
Note:
1. n = 1 or 2. Each output is assigned a frequency divider.
2. In the APLL, the selected T0/T4 DPLL output may be multiplied. E1 = 2.048 MHz, T1 = 1.544 MHz, E3 = 34.368 MHz, T3 = 44.736 MHz. The blank cell means the configuration is
reserved.
3. The 622.08 MHz and 311.04 MHz differential signals are only output on OUT1.
4. The 61.44 MHz, 30.72 MHz, 15.36 MHz, 7.68 MHz and 3.84 MHz outputs are only derived from T0 APLL.
(Output Divider)
0000
0001
0010
0011
0100
0101
0110
1000
1001
1010
1011
1100
1101
0111
1110
1111
1
77.76 MHz X 4 12E1 X 4
622.08 MHz
311.04 MHz
155.52 MHz
77.76 MHz
51.84 MHz
38.88 MHz
25.92 MHz
19.44 MHz
6.48 MHz
3
3
48E1
24E1
12E1
8E1
6E1
4E1
3E1
2E1
E1
16E1 X 4
64E1
32E1
16E1
8E1
4E1
2E1
E1
outputs on OUT1 & OUT2 if derived from T0/T4 APLL output
24T1 X 4
96T1
48T1
24T1
16T1
12T1
8T1
6T1
4T1
3T1
2T1
T1
Output is disabled (output high).
Output is disabled (output low).
16T1 X 4
37
64T1
32T1
16T1
8T1
4T1
2T1
T1
E3
E3
T3
T3
(26 MHz X 2)
52 MHz
26 MHz
13 MHz
GSM
2
(30.72 MHz X 10)
61.44 MHz
30.72 MHz
15.36 MHz
7.68 MHz
3.84 MHz
153.6 MHz
76.8 MHz
38.4 MHz
OBSAI
December 3, 2008
4
4
4
4
4
WAN PLL
(40 MHz)
20 MHz
10 MHz
5 MHz
GPS

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