IDT82V3255TFG IDT, Integrated Device Technology Inc, IDT82V3255TFG Datasheet - Page 41

• Manufacturer Part Number: IDT82V3255TFG
• Description: IC PLL WAN SMC STRATUM 3 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3255TFG

• Input: CMOS, LVDS, PECL
• Output: CMOS, LVDS, PECL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3255TFG

3.16
required to minimize supply noise modulation of the output clocks. The
common sources of power supply noise are switch power supplies and
the high switching noise from the outputs to the internal PLL. The
82V3255 provides separate VDDA power pins for the internal analog
PLL, VDD_DIFF for the differential output driver circuit and VDDD pins
for the core logic as well as I/O driver circuits.
ing regulator, the power supply output should be filtering with sufficient
bulk capacity to minimize ripple and 0.1 uF (0402 case size, ceramic)
caps to filter out the switching transients.
are handled individually. VDDD, VDD_DIFF and VDDA should be indi-
vidually connected to the power supply plane through vias, and bypass
capacitors should be used for each pin. Figure 12 illustrated how bypass
capacitor and ferrite bead should be connected to power pins.
Functional Description
IDT82V3255
To achieve optimum jitter performance, power supply filtering is
To minimize switching power supply noise generated by the switch-
For the 82V3255, the decoupling for VDDA, VDD_DIFF and VDDD
3.3V
SLF7028T-100M1R1
POWER SUPPLY FILTERING TECHNIQUES
10 µF
0.1 µF
3. 3V
0.1 µF
SLF7028T-100M1R1
0.1 µF
Figure 12. IDT82V3255 Power Decoupling Scheme
0.1 µF
10 µF
0.1 µF
0.1 µ F
0.1 µ F
0.1 µF
0.1 µF
41
0 .1 µF
0.1 µF
impedance. This can be achieved by using one 10 uF (1210 case size,
ceramic) and at least four 0.1 uF (0402 case size, ceramic) capacitors in
parallel. The 0.1 uF (0402 case size, ceramic) capacitors must be
placed right next to the VDDA and VDD_DIFF pins as close as possible.
Note that the 10 uF capacitor must be of 1210 case size, and it must be
ceramic for lowest ESR (Effective Series Resistance) possible. The 0.1
uF should be of case size 0402, this offers the lowest ESL (Effective
Series Inductance) to achieve low impedance towards the high speed
range.
uF (1210 case size, ceramic) capacitors are recommended. The 0.1 uF
capacitors should be placed as close to the VDDD pins as possible.
0.1 µF
The analog power supply VDDA and VDD_DIFF should have low
For VDDD, at least ten 0.1 uF (0402 case size, ceramic) and one 10
Please refer to evaluation board schematic for details.
0.1 µF
VDD _DIFF
VDDD
0.1 µF
VDDA
IDT 82 V3255
4, 14, 57
22
8, 9, 12, 32, 36, 38, 39, 45, 46 , 54
7, 10, 11, 31, 40, 53
1, 3, 15, 58
December 3, 2008
21
AGND
DGND
GND_DIFF
WAN PLL