IDT82V3255TFG IDT, Integrated Device Technology Inc, IDT82V3255TFG Datasheet - Page 13

• Manufacturer Part Number: IDT82V3255TFG
• Description: IC PLL WAN SMC STRATUM 3 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3255TFG

• Input: CMOS, LVDS, PECL
• Output: CMOS, LVDS, PECL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3255TFG

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Table 1: Pin Description
Pin Description
IDT82V3255
SONET/SDH
FF_SRCSW
EX_SYNC1
EX_SYNC2
EX_SYNC3
IN1_CMOS
IN2_CMOS
IN1_POS
IN1_NEG
IN2_POS
IN2_NEG
Name
OSCI
RST
PIN DESCRIPTION
Pin No.
13
64
48
28
33
35
29
30
23
24
25
26
6
pull-down
pull-down
pull-down
pull-down
pull-down
pull-down
pull-down
pull-up
I/O
I
I
I
I
I
I
I
I
I
I
I
PECL/LVDS
PECL/LVDS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Type
Frame Synchronization Input Signal
Global Control Signal
OSCI: Crystal Oscillator Master Clock
A nominal 12.8000 MHz clock provided by a crystal oscillator is input on this pin. It is the
master clock for the device.
FF_SRCSW: External Fast Selection Enable
During reset, this pin determines the default value of the EXT_SW bit (b4, 0BH)
EXT_SW bit determines whether the External Fast Selection is enabled.
High: The default value of the EXT_SW bit (b4, 0BH) is ‘1’ (External Fast selection is
enabled);
Low: The default value of the EXT_SW bit (b4, 0BH) is ‘0’ (External Fast selection is dis-
abled).
After reset, this pin selects an input clock pair for the T0 DPLL if the External Fast selection is
enabled:
High: Pair IN1_CMOS / IN1_DIFF is selected.
Low: Pair IN2_CMOS / IN2_DIFF is selected.
After reset, the input on this pin takes no effect if the External Fast selection is disabled.
SONET/SDH: SONET / SDH Frequency Selection
During reset, this pin determines the default value of the IN_SONET_SDH bit (b2, 09H):
High: The default value of the IN_SONET_SDH bit is ‘1’ (SONET);
Low: The default value of the IN_SONET_SDH bit is ‘0’ (SDH).
After reset, the value on this pin takes no effect.
RST: Reset
A low pulse of at least 50 µs on this pin resets the device. After this pin is high, the device will
still be held in reset state for 500 ms (typical).
EX_SYNC1: External Sync Input 1
A 2 kHz, 4 kHz or 8 kHz signal is input on this pin.
EX_SYNC2: External Sync Input 2
A 2 kHz, 4 kHz or 8 kHz signal is input on this pin.
EX_SYNC3: External Sync Input 3
A 2 kHz, 4 kHz or 8 kHz signal is input on this pin.
IN1_CMOS: Input Clock 1
A 2 kHz, 4 kHz, N x 8 kHz
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.
IN2_CMOS: Input Clock 2
A 2 kHz, 4 kHz, N x 8 kHz
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.
IN1_POS / IN1_NEG: Positive / Negative Input Clock 1
A 2 kHz, 4 kHz, N x 8 kHz
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz, 311.04 MHz or 622.08 MHz
clock is differentially input on this pair of pins. Whether the clock signal is PECL or LVDS is
automatically detected.
IN2_POS / IN2_NEG: Positive / Negative Input Clock 2
A 2 kHz, 4 kHz, N x 8 kHz
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz, 311.04 MHz or 622.08 MHz
clock is differentially input on this pair of pins. Whether the clock signal is PECL or LVDS is
automatically detected.
Input Clock
13
3
3
3
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
Description
1
December 3, 2008
WAN PLL
2
. The