IDT82V3255TFG IDT, Integrated Device Technology Inc, IDT82V3255TFG Datasheet - Page 36

• Manufacturer Part Number: IDT82V3255TFG
• Description: IC PLL WAN SMC STRATUM 3 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3255TFG

• Input: CMOS, LVDS, PECL
• Output: CMOS, LVDS, PECL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3255TFG

3.12
performance of the device output clocks.
/ T4_APLL_BW[1:0] bits respectively. The lower the bandwidth is, the
better the jitter and wander performance of the T0/T4 APLL output are.
T4 DPLL outputs, as selected by the T0_APLL_PATH[3:0] /
T4_APLL_PATH[3:0] bits respectively.
device output.
Table 24: Related Bit / Register in Chapter 3.12
Table 25: Outputs on OUT1 & OUT2 if Derived from T0/T4 DPLL Outputs
Functional Description
IDT82V3255
Note:
1. n = 1 or 2. Each output is assigned a frequency divider.
2. E1 = 2.048 MHz, T1 = 1.544 MHz, E3 = 34.368 MHz, T3 = 44.736 MHz. The blank cell means the configuration is reserved.
OUTn_DIVIDER[3:0]
T0_APLL_PATH[3:0]
T4_APLL_PATH[3:0]
(Output Divider)
T0_APLL_BW[1:0]
T4_APLL_BW[1:0]
A T0 APLL and a T4 APLL are provided for a better jitter and wander
The bandwidths of the T0/T4 APLL are set by the T0_APLL_BW[1:0]
The input of the T0/T4 APLL can be derived from one of the T0 and
Both the APLL and DPLL outputs are provided for selection for the
0000
0001
0010
0011
0100
0101
0110
1000
1001
1010
1011
1100
1101
0111
1110
1111
Bit
T0 / T4 APLL
1
77.76 MHz
64 kHz
400 Hz
T0_DPLL_APLL_PATH_CNFG
T4_DPLL_APLL_PATH_CNFG
8 kHz
2 kHz
1Hz
T0_T4_APLL_BW_CNFG
Register
12E1
12E1
6E1
3E1
2E1
E1
16E1
16E1
8E1
4E1
2E1
E1
outputs on OUT1 & OUT2 if derived from T0/T4 DPLL outputs
Address (Hex)
6A
55
60
24T1
24T1
12T1
6T1
4T1
3T1
2T1
T1
Output is disabled (output high).
Output is disabled (output low).
36
16T1
16T1
3.13
altogether.
3.13.1
OUT1_PECL_LVDS bit. OUT2 outputs a CMOS signal.
nals derived from the T0/T4 DPLL and T0/T4 APLL outputs, and the cor-
responding OUTn_PATH_SEL[3:0] bits (n = 1 or 2). The derived signal
can be from the T0/T4 DPLL and T0/T4 APLL outputs, as selected by
the corresponding OUTn_PATH_SEL[3:0] bits (n = 1 or 2). If the signal is
derived from one of the T0/T4 DPLL outputs, please refer to
the output frequency. If the signal is derived from the T0/T4 APLL output,
please refer to
the corresponding OUTn_INV bit (n = 1 or 2).
aligned with the T0/T4 selected input clock respectively every 125 µs
period.
8T1
4T1
2T1
T1
The device supports 2 output clocks and 2 frame sync output signals
The device provides 2 output clocks.
OUT1 outputs a PECL or LVDS signal, as selected by the
The outputs on OUT1 and OUT2 are variable, depending on the sig-
The outputs on OUT1 and OUT2 can be inverted, as determined by
Both the output clocks derived from T0/T4 selected input clock are
OUTPUT CLOCKS & FRAME SYNC SIGNALS
OUTPUT CLOCKS
E3
E3
Table 26
for the output frequency.
T3
T3
(26 MHz)
13 MHz
2
GSM
(30.72 MHz)
15.36 MHz
OBSAI
December 3, 2008
Table 25
WAN PLL
(40 MHz)
GPS
20
10
5
for