IDT82V3255TFG IDT, Integrated Device Technology Inc, IDT82V3255TFG Datasheet - Page 8

• Manufacturer Part Number: IDT82V3255TFG
• Description: IC PLL WAN SMC STRATUM 3 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3255TFG

• Input: CMOS, LVDS, PECL
• Output: CMOS, LVDS, PECL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3255TFG

List of Figures
Figure 1. Functional Block Diagram ............................................................................................................................................................................ 11
Figure 2. Pin Assignment (Top View) .......................................................................................................................................................................... 12
Figure 3. Pre-Divider for An Input Clock ..................................................................................................................................................................... 19
Figure 4. Input Clock Activity Monitoring ..................................................................................................................................................................... 20
Figure 5. External Fast Selection ................................................................................................................................................................................ 22
Figure 6. T0 Selected Input Clock vs. DPLL Automatic Operating Mode ................................................................................................................... 29
Figure 7. T4 Selected Input Clock vs. DPLL Automatic Operating Mode ................................................................................................................... 30
Figure 8. On Target Frame Sync Input Signal Timing ................................................................................................................................................. 38
Figure 9. 0.5 UI Early Frame Sync Input Signal Timing .............................................................................................................................................. 38
Figure 10. 0.5 UI Late Frame Sync Input Signal Timing .............................................................................................................................................. 39
Figure 11. 1 UI Late Frame Sync Input Signal Timing ................................................................................................................................................. 39
Figure 12. IDT82V3255 Power Decoupling Scheme ................................................................................................................................................... 41
Figure 13. Line Card Application ................................................................................................................................................................................. 42
Figure 14. Serial Read Timing Diagram (CLKE Asserted Low) ................................................................................................................................... 43
Figure 15. Serial Read Timing Diagram (CLKE Asserted High) .................................................................................................................................. 43
Figure 16. Serial Write Timing Diagram ....................................................................................................................................................................... 44
Figure 17. JTAG Interface Timing Diagram ................................................................................................................................................................. 45
Figure 18. Recommended PECL Input Port Line Termination .................................................................................................................................. 114
Figure 19. Recommended PECL Output Port Line Termination ................................................................................................................................ 114
Figure 20. Recommended LVDS Input Port Line Termination .................................................................................................................................. 116
Figure 21. Recommended LVDS Output Port Line Termination ................................................................................................................................ 116
Figure 22. Output Wander Generation ...................................................................................................................................................................... 120
Figure 23. Input / Output Clock Timing ...................................................................................................................................................................... 121
Figure 24. 64-Pin PP Package Dimensions (a) (in Millimeters) ................................................................................................................................. 127
Figure 25. 64-Pin PP Package Dimensions (b) (in Millimeters) ................................................................................................................................. 128
Figure 26. 64-Pin EDG Package Dimensions (a) (in Millimeters) .............................................................................................................................. 129
Figure 27. 64-Pin EDG Package Dimensions (b) (in Millimeters) .............................................................................................................................. 130
Figure 28. EDG64 Recommended Land Pattern with Exposed Pad (in Millimeters) ................................................................................................. 131
List of Figures
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December 3, 2008