DS3106LN+ Maxim Integrated Products, DS3106LN+ Datasheet - Page 67

• Manufacturer Part Number: DS3106LN+
• Description: IC TIMING LINE CARD 64-LQFP
• Manufacturer: Maxim Integrated Products
• Type: Timing Card ICr

Specifications of DS3106LN+

• Input: CMOS, LVDS, LVPECL, TTL
• Output: CMOS, LVDS, LVPECL, TTL
• Frequency - Max: 312.5MHz
• Voltage - Supply: 1.62 V ~ 1.98 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Frequency-max: 312.5MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Low-Frequency Input Clock Noise Window (NW). For 2kHz, 4kHz, or 8kHz input clocks, this configuration
bit enables a 5% tolerance noise window centered around the expected clock edge location. Noise-induced edges
outside this window are ignored, reducing the possibility of phase hits on the output clocks. This only applies to the
T0 DPLL and should be enabled only when the T0 DPLL is locked to an input and the 180 phase detector is being
used (TEST1.D180=0).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: The PHASE1 and PHASE2 registers must be read consecutively. See Section 8.3.
Bits 7 to 0: Current DPLL Phase (PHASE[7:0]). The full 16-bit PHASE[15:0] field spans this register and the
PHASE2
detector. The value is the output of the phase averager. The averaged phase difference in degrees is equal to
PHASE  0.707. See Section 7.7.6.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Current DPLL Phase (PHASE[15:8]). See the
19-4629; Rev 4; 8/10
____________________________________________________________________________________________ DS3106
0 = All edges are recognized by the T0 DPLL.
1 = Only edges within the 5% tolerance window are recognized by the T0 DPLL.
register. PHASE is a two’s-complement signed integer that indicates the current value of the phase
NW
7
0
7
0
7
0
—
6
0
6
0
6
0
PHMON
Phase Monitor Register
76h
PHASE1
Phase Register 1
77h
PHASE2
Phase Register 2
78h
—
5
0
5
0
5
0
—
4
4
0
4
0
0
PHASE[15:8]
PHASE[7:0]
PHASE1
—
3
0
3
0
register description.
3
0
—
2
0
2
0
2
1
—
1
0
1
0
1
1
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—
0
0
0
0
0
0