DS3106LN+ Maxim Integrated Products, DS3106LN+ Datasheet - Page 59

• Manufacturer Part Number: DS3106LN+
• Description: IC TIMING LINE CARD 64-LQFP
• Manufacturer: Maxim Integrated Products
• Type: Timing Card ICr

Specifications of DS3106LN+

• Input: CMOS, LVDS, LVPECL, TTL
• Output: CMOS, LVDS, LVPECL, TTL
• Frequency - Max: 312.5MHz
• Voltage - Supply: 1.62 V ~ 1.98 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Frequency-max: 312.5MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: MFSYNC Enable (MFSEN). This configuration bit enables the 2kHz output on the MFSYNC pin. See Section
7.8.2.5.
Bit 6: FSYNC Enable (FSEN). This configuration bit enables the 8kHz output on the FSYNC pin. See Section
7.8.2.5.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 3 to 0: T4 APLL Frequency (T4FREQ[3:0]). When T0CR1:T4APT0 = 0, this field configures the T4 APLL
DFS frequency. The T4 APLL DFS frequency affects the frequency of the T4 APLL which, in turn, affects the
available output frequencies on the output clock pins (see the
of this field is controlled by the O6F[2:0] and O3F[2:0] pins as described in
19-4629; Rev 4; 8/10
____________________________________________________________________________________________ DS3106
0 = Disabled, driven low
1 = Enabled, output is 2kHz
0 = Disabled, driven low
1 = Enabled, output is 8kHz
T4FREQ[3:0]
1101–1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
MFSEN
—
7
1
7
0
T4 APLL DFS FREQUENCY
25.248MHz (4 x 6312kHz)
40.000MHz (4 x 10MHz)
26.000MHz (2 x 13MHz)
FSEN
37.056MHz (24 x DS1)
24.704MHz (16 x DS1)
62.500MHz (GbE  16)
30.720MHz (3 x 10.24)
APLL output disabled
24.576MHz (12 x E1)
32.768MHz (16 x E1)
68.736MHz (2 x E3)
—
6
1
6
0
44.736MHz (DS3)
{unused values}
OCR4
Output Configuration Register 4
63h
T4CR1
T4 DPLL Configuration Register 1
64h
77.76MHz
—
5
0
0
5
0
—
4
0
4
0
0
T4 APLL FREQUENCY (4 x T4 APLL DFS)
OCR
100.992MHz (16 x 6312kHz)
311.04MHz (4 x 77.76MHz)
160.000MHz (16 x 10MHz)
104.000MHz (8 x 13MHz)
registers). See Section 7.8.2. The default value
122.880MHz (12 x 10.24)
148.224MHz (96 x DS1)
250.000MHz (GbE  4)
98.816MHz (64 x DS1)
178.944MHz (4 x DS3)
3
Disabled, output is low
3
0
0
131.072MHz (64 x E1)
98.304MHz (48 x E1)
274.944MHz (8 x E3)
{unused values}
Table
7-15.
2
2
0
0
T4FREQ[3:0]
see below
1
1
0
0
59 of 87
0
0
0
0