DS3106LN+ Maxim Integrated Products, DS3106LN+ Datasheet
DS3106LN+
Specifications of DS3106LN+
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DS3106LN+ Summary of contents
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... OC6 LVDS/LVPECL FSYNC MFSYNC DS3106LN DS3106LN+ +Denotes a lead(Pb)-free/RoHS-compliant package. SPI is a trademark of Motorola, Inc. DS3106 Programmable PLL Bandwidth: 18Hz to 400Hz Manual Reference Switching Holdover on Loss of All Input References Frequency Conversion Among SONET/SDH, PDH, Ethernet, Wireless, and CMTS Rates CMOS/TTL Signal Format (≤ ...
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DS3106 1. STANDARDS COMPLIANCE ..........................................................................................................6 2. APPLICATION EXAMPLE ...............................................................................................................7 3. BLOCK DIAGRAM ...........................................................................................................................7 4. DETAILED DESCRIPTION ..............................................................................................................8 5. DETAILED FEATURES ...................................................................................................................9 5 NPUT LOCK EATURES 5.2 DPLL F .............................................................................................................................9 EATURES 5.3 O APLL F UTPUT EATURES ...
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DS3106 9. JTAG TEST ACCESS PORT AND BOUNDARY SCAN ...............................................................70 9.1 JTAG D ......................................................................................................................70 ESCRIPTION 9.2 JTAG TAP C ONTROLLER 9.3 JTAG I R NSTRUCTION EGISTER AND 9.4 JTAG T R ................................................................................................................74 EST EGISTERS 10. ELECTRICAL CHARACTERISTICS..............................................................................................75 10.1 DC ...
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DS3106 Figure 2-1. Typical Application Example ..................................................................................................................... 7 Figure 3-1. Block Diagram ........................................................................................................................................... 7 Figure 7-1. DPLL Block Diagram ............................................................................................................................... 18 Figure 7-2. T0 DPLL State Transition Diagram ......................................................................................................... 20 Figure 7-3. FSYNC 8kHz Options.............................................................................................................................. 32 Figure 7-4. SPI ...
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DS3106 Table 1-1. Applicable Telecom Standards................................................................................................................... 6 Table 6-1. Input Clock Pin Descriptions .................................................................................................................... 10 Table 6-2. Output Clock Pin Descriptions.................................................................................................................. 10 Table 6-3. Global Pin Descriptions ............................................................................................................................ 11 Table 6-4. SPI Bus Mode Pin Descriptions ............................................................................................................... 12 Table ...
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DS3106 1. Standards Compliance Table 1-1. Applicable Telecom Standards SPECIFICATION ANSI T1.101 Synchronization Interface Standard, 1999 TIA/EIA-644-A Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits, 2001 ETSI Transmission and Multiplexing (TM); Generic requirements of transport functionality of ...
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DS3106 2. Application Example Figure 2-1. Typical Application Example 19.44 MHz IC3 From Master Timing Card IC4 19.44 MHz From Slave Timing Card 3. Block Diagram Figure 3-1. Block Diagram IC3 IC4 JTRST* JTMS JTAG JTCLK JTDI JTDO 19-4629; ...
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DS3106 4. Detailed Description Figure 3-1 illustrates the blocks described in this section and how they relate to one another. Section detailed feature list. The DS3106 is a complete line card timing IC. At the core of this device ...
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DS3106 5. Detailed Features 5.1 Input Clock Features Two programmable-frequency CMOS/TTL input clocks Input clocks accept any multiple of 2kHz up to 125MHz All input clocks are constantly monitored by programmable activity monitors 5.2 DPLL Features ...
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DS3106 6. Pin Descriptions Table 6-1. Input Clock Pin Descriptions (1) (2) PIN NAME TYPE Reference Clock. Connect to a 12.800MHz, high-accuracy, high-stability, low-noise local REFCLK I oscillator (XO or TCXO). See Section 7.3. Input Clock 3. CMOS/TTL. Programmable ...
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DS3106 Table 6-3. Global Pin Descriptions (1) (2) PIN NAME TYPE Reset (Active Low). When this global asynchronous reset is pulled low, all internal circuitry is reset to default values. The device is held in reset as long as ...
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DS3106 (1) (2) PIN NAME TYPE SONET/SDH Frequency Select Input/General-Purpose I/O 4. When RST goes high the state of this pin sets the reset-default state of MCR3:SONSDH, MCR6:DIG1SS, and MCR6:DIG2SS. After RST goes high, this pin can be used ...
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DS3106 Table 6-6. Power-Supply Pin Descriptions (1) (2) PIN NAME TYPE Core Power Supply. 1.8V 10%. VDD P I/O Power Supply. 3.3V 5%. VDDIO P VSS P Ground Reference Power Supply for OC6 Digital Logic. 1.8V 10%. AVDD_DL P ...
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DS3106 7. Functional Description 7.1 Overview The DS3106 has two input clocks, two output clocks, and a high-performance DPLL known as T0. two input clocks are CMOS/TTL (5V tolerant) and can accept signals from 2kHz to 125MHz. Each input ...
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DS3106 7.4 Input Clock Configuration The DS3106 has two input clocks: IC3 and IC4. including signal format and available frequencies. The device tolerates a wide range of duty cycles on input clocks, out to a minimum high time or ...
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DS3106 7.4.2.1 Direct Lock Mode In direct lock mode, the T0 DPLL locks to the selected reference at the frequency specified in the corresponding I CR register. Direct lock mode can only be used for input clocks with these ...
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DS3106 between events and no alarm is declared. When events occur close enough together, the accumulator increments faster than it can decay and eventually reaches the alarm threshold. After an alarm has been declared, if events occur infrequently enough, ...
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DS3106 7.7 DPLL Architecture and Configuration The T0 DPLL is a digital PLL with separate analog PLLs (APLLs) as output stages as well as some outputs that are not cleaned APLL. This architecture combines the benefits ...
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DS3106 Digital PLLs have two key benefits: (1) stable, repeatable performance that is insensitive to process variations, temperature, and voltage; and (2) flexible behavior that is easily programmed through the configuration registers. DPLLs use digital frequency synthesis (DFS) to ...
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DS3106 Figure 7-2. T0 DPLL State Transition Diagram SELECTED REFERENCE SWITCH SELECTED REFERENCE PHASE-LOCKED > 2s SELECTED REFERENCE SWITCH PRE-LOCKED 2 (101) Note 1: Phase lock is declared internally when the DPLL has maintained phase lock continuously for approximately ...
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DS3106 7.7.1.3 Locked State The T0 DPLL state machine can reach the locked state from the prelocked, prelocked 2, or loss-of-lock states when the DPLL has locked to the selected reference for at least 2 seconds (see Section 7.7.5). ...
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DS3106 7.7.1.7 Mini-Holdover When the selected reference fails, the fast activity monitor (Section 7.5.3) isolates the T0 DPLL from the reference within one or two clock cycles to avoid adverse effects on the DPLL frequency. When this fast isolation ...
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DS3106 The T0 DPLL phase detectors can be configured for normal phase/frequency locking (360 capture) or nearest edge phase locking (180 capture). With nearest edge detection the phase detectors are immune to occasional missing clock cycles. The DPLL automatically ...
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DS3106 7.7.6 Frequency and Phase Measurement Accurate measurement of frequency and phase can be accomplished using the T0 DPLL. The REFCLK signal accuracy after being adjusted with MCLKFREQ is used for the frequency reference. DPLL frequency measurements can be ...
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DS3106 7.8.1 Signal Format Configuration Output clock OC6 is an LVDS-compatible, LVPECL level-compatible outputs. The type of output can be selected or the output can be disabled using the OC6SF configuration bits in the mode generates a differential signal ...
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DS3106 7.8.2.3 OC3 and OC6 Configuration The following is a step-by-step procedure for configuring the frequencies of output clocks OC3 and OC6: Use Table 7-8 to select a set of output frequencies for each APLL, T0 and T4. Each ...
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DS3106 Table 7-8. APLL Frequency to Output Frequencies (T0 APLL and T4 APLL) APLL APLL/ APLL/ FREQUENCY 2 4 312.5 156.25 — 311.04 155.52 77.76 62.208 274.944 137.472 68.376 250 125 62.5 178.944 89.472 44.736 160 80 40 148.224 ...
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DS3106 Table 7-11. T4 APLL Frequency Configuration T4 APLL T4 APLL DFS FREQUENCY FREQUENCY (MHz) (MHz) Disabled 77.76 311.04 77.76 98.304 24.576 131.072 32.768 148.224 37.056 98.816 24.704 274.944 68.736 178.944 44.736 100.992 25.248 250.000 62.500 122.880 30.720 160.000 ...
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DS3106 Table 7-13. Standard Frequencies for Programmable Outputs FREQUENCY (MHz) 2kHz 8kHz 1.536 Not OC6 from T0 APLL 1.544 Not OC6 from DIG2 1.544 Not OC6 from T0 APLL 1.578 Not OC6 from T0 APLL 2.048 Not OC6 from ...
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DS3106 FREQUENCY (MHz) 16.832 17.184 18.528 19.440 OC3 only 19.440 20.000 20.800 22.368 24.576 24.576 24.704 24.704 25.000 OC3 only 25.248 25.920 26.000 30.720 31.104 OC3 only 31.250 31.250 32.000 32.768 34.368 37.056 38.880 40.000 44.736 49.152 Not OC3 ...
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DS3106 FREQUENCY (MHz) 274.944 OC6 only 311.040 OC6 only 312.500 OC6 only from T0 APLL2 7.8.2.4 OC3 and OC6 Default Frequency Select Pins There are two sets of frequency select pins, O3F[2:0] and O6F[2:0], that control the reset default ...
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DS3106 Table 7-17. OC3 Default Frequency Configuration FREQUENCY O3F[2:0] SONSDH (MHz) 000 8.192 001 1 6.176 001 0 8.192 001 1 12.352 010 0 68.736 010 1 22.368 011* X 19.44 100 X 25.92 101 X ...
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DS3106 77.76MHz, any multiple of 8kHz up to 311.04MHz, and any multiple of 10kHz up to 388.79MHz. (An APLL must be used to achieve frequencies above 77.76MHz.) Any of the programmable output clocks can be configured to output the ...
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DS3106 Early Termination of Bus Transactions. The bus master can terminate SPI bus transactions at any time by pulling CS high. In response to early terminations, the DS3106 resets its SPI interface logic and waits for the start of ...
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DS3106 Figure 7-4. SPI Clock Phase Options CS SCLK CPHA = 0 SCLK CPHA = 1 SDI/SDO Figure 7-5. SPI Bus Transactions Single-Byte Write CS R/W Register Address Burst SDI 0 (Write) SDO Single-Byte Read CS R/W Register Address ...
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DS3106 7.10 Reset Logic The device has three reset controls: the RST pin, the RST bit in MCR1, and the JTAG reset pin JTRST. The RST pin asynchronously resets the entire device, except for the JTAG logic. When the ...
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DS3106 8. Register Descriptions The DS3106 has an overall address range from 000h to 1FFh. each register, bit 7 is the MSB and bit 0 is the LSB. Register addresses not listed and bits marked “—“ are reserved and ...
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DS3106 8.4 Register Definitions Table 8-1. Register Map Note: Register names are hyperlinks to register definitions. Underlined fields are read-only. ADDR REGISTER BIT 7 00h ID1 01h ID2 02h REV 03h TEST1 PALARM 05h MSR1 — 06h MSR2 STATE ...
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DS3106 ADDR REGISTER BIT 7 67h T0LBW — 69h T0ABW — 6Bh T0CR2 — 6Dh T0CR3 PD2EN 6Eh GPCR GPIO4D GPIO3D 6Fh GPSR — 73h PHLIM1 FLEN NALOL 74h PHLIM2 CLEN MCPDEN USEMCPD 76h PHMON NW 77h PHASE1 78h ...
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DS3106 Register Name: ID1 Register Description: Device Identification Register, LSB Register Address: 00h Bit # 7 6 Name Default 0 0 Bits Device ID (ID[7:0]). ID[15:0] = 0C22h = 3106 decimal. Register Name: ID2 Register Description: ...
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DS3106 Register Name: TEST1 Register Description: Test Register 1 (Not Normally Used) Register Address: 03h Bit # 7 6 Name PALARM D180 Default 0 0 Bit 7: Phase Alarm (PALARM). This real-time status bit indicates the state of the ...
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DS3106 Register Name: MSR1 Register Description: Master Status Register 1 Register Address: 05h Bit # 7 6 Name — — Default 1 0 Bits 3 and 2: Input Clock Status Change (IC[3:2]). Each of these latched status bits is ...
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DS3106 Register Name: OPSTATE Register Description: Operating State Register Register Address: 09h Bit # 7 6 Name — — Default 1 0 Bit 5: T0 DPLL Frequency Soft Alarm (T0SOFT). This real-time status bit indicates whether the T0 DPLL ...
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DS3106 Register Name: FREQ1 Register Description: Frequency Register 1 Register Address: 0Ch Bit # 7 6 Name Default 0 0 Note: The FREQ1, FREQ2, and FREQ3 registers must be read consecutively. See Section 8.3. Bits Current ...
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DS3106 Register Name: VALSR1 Register Description: Input Clock Valid Status Register 1 Register Address: 0Eh Bit # 7 6 Name — — Default 0 0 Bits 3 and 2: Input Clock Valid Status (IC[3:2]). Each of these real-time status ...
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DS3106 Register Name: ICR3, ICR4 Register Description: Input Configuration Register 3, 4 Register Address: 22h, 23h Bit # 7 6 Name DIVN LOCK8K Default 0 0 Note: These registers are identical in function. ICRx is the control register for ...
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DS3106 Register Name: MCR1 Register Description: Master Configuration Register 1 Register Address: 32h Bit # 7 6 Name RST — Default 0 0 Bit 7: Device Reset (RST). When this bit is high the entire device is held in ...
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DS3106 Register Name: MCR3 Register Description: Master Configuration Register 3 Register Address: 34h Bit # 7 6 Name — — Default 1 1 Bit 5: Local Oscillator Edge (XOEDGE). This bit specifies the significant clock edge of the local ...
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DS3106 Register Name: MCR7 Register Description: Master Configuration Register 7 Register Address: 39h Bit # 7 6 Name DIG2F[1:0] Default 0 0 Bits 7 and 6: Digital2 Frequency (DIG2F[1:0]). This field, MCR6:DIG2SS, and MCR6:DIG2AF configure the frequency of the ...
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DS3106 Register Name: MCR8 Register Description: Master Configuration Register 8 Register Address: 3Ah Bit # 7 6 Name — — Default 0 0 For Rev A2 devices, in LVPECL mode the differential output voltage will be higher than the ...
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DS3106 Register Name: MCLK1 Register Description: Master Clock Frequency Adjustment Register 1 Register Address: 3Ch Bit # 7 6 Name Default 1 0 Note: The MCLK1 and MCLK2 registers must be read consecutively and written consecutively. See Section 8.3. ...
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DS3106 Register Name: DLIMIT1 Register Description: DPLL Frequency Limit Register 1 Register Address: 41h Bit # 7 6 Name Default 1 1 Note: The DLIMIT1 and DLIMIT2 registers must be read consecutively and written consecutively. See Section 8.3. Bits ...
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DS3106 Register Name: IER1 Register Description: Interrupt Enable Register 1 Register Address: 43h Bit # 7 6 Name — — Default 0 0 Bits 3 and 2: Interrupt Enable for Input Clock Status Change (IC[3:2]). Each of these bits ...
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DS3106 Register Name: DIVN1 Register Description: DIVN Register 1 Register Address: 46h Bit # 7 6 Name Default 1 1 Note: The DIVN1 and DIVN2 registers must be read consecutively and written consecutively. See Section 8.3. Bits 7 to ...
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DS3106 Register Name: DLIMIT3 Register Description: DPLL Frequency Limit Register 3 Register Address: 4Dh Bit # 7 6 Name FLLOL Default 1 0 Bit 7: Frequency Limit Loss-of-Lock (FLLOL). When this bit is set to 1, the T0 DPLL ...
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DS3106 Register Name: LB0U Register Description: Leaky Bucket 0 Upper Threshold Register Register Address: 50h Bit # 7 6 Name Default 0 0 Bits Leaky Bucket 0 Upper Threshold (LB0U[7:0]). When the leaky bucket accumulator is ...
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DS3106 Register Name: OCR2 Register Description: Output Configuration Register 2 Register Address: 61h Bit # 7 6 Name 0 0 Default 0 0 Bits Output Frequency of OC3 (OFREQ3[3:0]). This field specifies the frequency of output ...
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DS3106 Register Name: OCR3 Register Description: Output Configuration Register 3 Register Address: 62h Bit # 7 6 Name OFREQ6[3:0] Default see below Bits Output Frequency of OC6 (OFREQ6[3:0]). This field specifies the frequency of output clock ...
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DS3106 Register Name: OCR4 Register Description: Output Configuration Register 4 Register Address: 63h Bit # 7 6 Name MFSEN FSEN Default 1 1 Bit 7: MFSYNC Enable (MFSEN). This configuration bit enables the 2kHz output on the MFSYNC pin. ...
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DS3106 Register Name: T0CR1 Register Description: T0 DPLL Configuration Register 1 Register Address: 65h Bit # 7 6 Name — T4APT0 Default 0 0 Bit 6: T4 APLL Source from T0 (T4APT0). When this bit is set to 0, ...
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DS3106 Register Name: T0LBW Register Description: T0 DPLL Locked Bandwidth Register Register Address: 67h Bit # 7 6 Name 0 0 Default 0 0 Bits 4 and 3: Reserved Bit 1 and 2 (RSV[1:2]). These bits are reserved for ...
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DS3106 Register Name: T0CR2 Register Description: T0 Configuration Register 2 Register Address: 6Bh Bit # 7 6 Name — Default 0 0 Bits Phase Detector 2 Gain, 8kHz (PD2G8K[2:0]). This field specifies the gain of the ...
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DS3106 Register Name: GPCR Register Description: GPIO Configuration Register Register Address: 6Eh Bit # 7 6 Name GPIO4D GPIO3D Default 0 0 Bit 7: GPIO4 Direction (GPIO4D). This bit configures the data direction for the GPIO4 pin. When GPIO4 ...
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DS3106 Register Name: GPSR Register Description: GPIO Status Register Register Address: 6Fh Bit # 7 6 Name — — Default 0 0 Bit 3: GPIO4 State (GPIO4). This bit indicates the current state of the GPIO4 pin ...
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DS3106 Register Name: PHLIM1 Register Description: Phase Limit Register 1 Register Address: 73h Bit # 7 6 Name FLEN NALOL Default 1 0 Bit 7: Fine Phase Limit Enable (FLEN). This configuration bit enables the fine phase limit specified ...
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DS3106 Register Name: PHLIM2 Register Description: Phase Limit Register 2 Register Address: 74h Bit # 7 6 Name CLEN MCPDEN Default 1 1 Bit 7: Coarse Phase Limit Enable (CLEN). This configuration bit enables the coarse phase limit specified ...
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DS3106 Register Name: PHMON Register Description: Phase Monitor Register Register Address: 76h Bit # 7 6 Name NW — Default 0 0 Bit 7: Low-Frequency Input Clock Noise Window (NW). For 2kHz, 4kHz, or 8kHz input clocks, this configuration ...
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DS3106 Register Name: FSCR1 Register Description: Frame-Sync Configuration Register 1 Register Address: 7Ah Bit # 7 6 Name — — Default 0 0 Bit 3: 8kHz Invert (8KINV). When this bit is set to 1, the 8kHz signal on ...
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DS3106 Register Name: INTCR Register Description: Interrupt Configuration Register Register Address: 7Dh Bit # 7 6 Name — — Default 0 0 Bit 3: INTREQ Pin Mode (LOS). When GPO = 0, this bit selects the function of the ...
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DS3106 9. JTAG Test Access Port and Boundary Scan 9.1 JTAG Description The DS3106 supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. the following items, which meet the requirements ...
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DS3106 9.2 JTAG TAP Controller State Machine Description This section discusses the operation of the TAP controller state machine. The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge ...
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DS3106 Exit1-IR. A rising edge on JTCLK with JTMS low puts the controller in the Pause-IR state. If JTMS is high on the rising edge of JTCLK, the controller enters the Update-IR state and terminates the scanning process. Pause-IR. ...
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DS3106 9.3 JTAG Instruction Register and Instructions The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the TAP controller enters the Shift-IR state, the instruction shift register ...
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DS3106 9.4 JTAG Test Registers IEEE 1149.1 requires a minimum of two test registers—the bypass register and the boundary scan register. An optional test register, the identification register, has been included in the device design used with ...
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DS3106 10. Electrical Characteristics ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin with Respect to V Supply Voltage Range (V ) with Respect Supply Voltage Range (V ) with Respect to V DDIO Ambient Operating Temperature ...
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DS3106 Table 10-3. CMOS/TTL Pins = 1.8V 10 3.3V 5 DDIO PARAMETER Input High Voltage Input Low Voltage Input Leakage Input Leakage, Pins with Internal Pullup Resistor (50k typ) Input Leakage, Pins with Internal ...
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DS3106 Table 10-5. LVPECL Level-Compatible Output Pins = 1.8V 10 3.3V 5 DDIO PARAMETER Differential Output Voltage Output Offset (Common Mode) Voltage Difference in Magnitude of Output Differential Voltage for Complementary States Note 1: ...
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DS3106 10.2 Input Clock Timing Table 10-6. Input Clock Timing = 1.8V 10 3.3V 5 DDIO PARAMETER SYMBOL Input Clock Duty Cycle 10.3 Output Clock Timing Table 10-7. Input Clock to Output Clock Delay ...
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DS3106 10.4 SPI Interface Timing Table 10-9. SPI Interface Timing = 1.8V 10 3.3V 5 DDIO PARAMETER (Note 1) SCLK Frequency SCLK Cycle Time CS Setup to First SCLK Edge CS Hold Time After ...
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DS3106 Figure 10-3. SPI Interface Timing Diagram CPHA = SUC CYC SCLK, CPOL=0 t CLKH t SCLK, CLKL CPOL SUI HDI SDI SDO CPHA = SUC CYC SCLK, CPOL=0 ...
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DS3106 10.5 JTAG Interface Timing Table 10-10. JTAG Interface Timing = 1.8V 10 3.3V 5 DDIO PARAMETER JTCLK Clock Period JTCLK Clock High/Low Time (Note 1) JTCLK to JTDI, JTMS Setup Time JTCLK to ...
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DS3106 10.6 Reset Pin Timing Table 10-11. Reset Pin Timing = 1.8V 10 3.3V 5 DDIO PARAMETER RST Low Time (Note 1) SONSDH, IPF[2:0], O3F[2:0], O6F[2:0] Setup Time to RST SONSDH, IPF[2:0], O3F[2:0], O6F[2:0] ...
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DS3106 11. Pin Assignments Table 11-1 lists pin assignments sorted in alphabetical order by pin name. arranged by pin number. Table 11-1. Pin Assignments Sorted by Signal Name PIN NAME PIN NUMBER AVDD_DL 59 AVDD_PLL1 AVDD_PLL2 AVDD_PLL3 AVDD_PLL4 11 ...
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DS3106 Figure 11-1. Pin Assignment Diagram VSS 1 TEST 2 AVSS_PLL1 3 AVDD_PLL1 4 INTREQ/LOS 5 REFCLK 6 AVDD_PLL2 7 AVSS_PLL2 8 AVDD_PLL3 9 AVSS_PLL3 10 AVDD_PLL4 11 AVSS_PLL4 12 SRCSW 13 VDDIO 14 VSS 15 VSS 16 19-4629; ...
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DS3106 12. Package Information For the latest package outline information and land patterns www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, ...
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DS3106 14. Acronyms and Abbreviations AIS Alarm Indication Signal AMI Alternate Mark Inversion APLL Analog Phase-Locked Loop BITS Building Integrated Timing Supply BPV Bipolar Violation DFS Digital Frequency Synthesis DPLL Digital Phase-Locked Loop ESF Extended Superframe EXZ Excessive Zeros ...
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... SRFAIL pin description to indicate state is high impedance when 7.7.5 deleted sentence that said the hard and soft limits have hysteresis. Maxim is a registered trademark of Maxim Integrated Products. Table 7-17 to match actual device PAGES CHANGED — ...