DS3106LN+ Maxim Integrated Products, DS3106LN+ Datasheet - Page 55

• Manufacturer Part Number: DS3106LN+
• Description: IC TIMING LINE CARD 64-LQFP
• Manufacturer: Maxim Integrated Products
• Type: Timing Card ICr

Specifications of DS3106LN+

• Input: CMOS, LVDS, LVPECL, TTL
• Output: CMOS, LVDS, LVPECL, TTL
• Frequency - Max: 312.5MHz
• Voltage - Supply: 1.62 V ~ 1.98 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Frequency-max: 312.5MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Frequency Limit Loss-of-Lock (FLLOL). When this bit is set to 1, the T0 DPLL internally declares loss-of-
lock when the hard frequency limit in the
Bits 6 to 0: DPLL Soft Frequency Limit (SOFTLIM[6:0]). This field is an unsigned integer that specifies the soft
frequency limit for the T0 DPLL. The soft limit is only used for monitoring; exceeding this limit does not cause loss-
of-lock. The limit in ppm is SOFTLIM[6:0]  0.628. The default value is 8.79ppm. When the T0 DPLL frequency
reaches the soft limit, the T0SOFT status bit is set in the
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 6: Interrupt Enable for Holdover Frequency Ready (HORDY). This bit is an interrupt enable for the HORDY
bit in the
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 5: Alternate Output Frequency Mode Select 6 (AOF6). This bit controls the decoding of the OCR3.OFREQ6
field for the OC6 pin.
Bit 2: Alternate Output Frequency Mode Select 3 (AOF3). This bit controls the decoding of the OCR2.OFREQ3
field for the OC3 pin.
19-4629; Rev 4; 8/10
____________________________________________________________________________________________ DS3106
0 = DPLL declares loss-of-lock normally.
1 = DPLL also declares loss-of-lock when the hard frequency limit is reached.
0 = Mask the interrupt
1 = Enable the interrupt
0 = Standard decodes
1 = Alternate decodes
0 = Standard decodes
1 = Alternate decodes
MSR4
FLLOL
register.
—
—
7
1
7
0
7
0
HORDY
—
6
0
6
0
6
0
DLIMIT3
DPLL Frequency Limit Register 3
4Dh
IER4
Interrupt Enable Register 4
4Eh
OCR5
Output Configuration Register 1
4Fh
DLIMIT1
AOF6
—
5
0
5
0
5
0
and
DLIMIT2
—
—
4
0
4
0
4
0
OPSTATE
SOFTLIM[6:0]
registers is reached. See Section 7.7.5.
register. See Section 7.7.5.
—
—
3
1
3
0
3
0
AOF3
—
2
1
2
0
2
0
—
—
1
1
1
0
1
0
55 of 87
—
—
0
0
0
0
0
0