DS3106LN+ Maxim Integrated Products, DS3106LN+ Datasheet - Page 12

• Manufacturer Part Number: DS3106LN+
• Description: IC TIMING LINE CARD 64-LQFP
• Manufacturer: Maxim Integrated Products
• Type: Timing Card ICr

Specifications of DS3106LN+

• Input: CMOS, LVDS, LVPECL, TTL
• Output: CMOS, LVDS, LVPECL, TTL
• Frequency - Max: 312.5MHz
• Voltage - Supply: 1.62 V ~ 1.98 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Frequency-max: 312.5MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 6-4. SPI Bus Mode Pin Descriptions
See Section
Table 6-5. JTAG Interface Pin Descriptions
See Section
19-4629; Rev 4; 8/10
____________________________________________________________________________________________ DS3106
INTREQ/LOS
PIN NAME
PIN NAME
PIN NAME
SONSDH/
GPIO4
JTCLK
JTRST
CPHA
SCLK
JTDO
JTMS
SDO
JTDI
SDI
CS
7.9
9
for functional description and Section
(1)
(1)
(1)
for functional description and Section
TYPE
TYPE
TYPE
IO
I
I
I
I
O
O
O
PU
PU
PU
PU
I
I
I
I
PD
3
3
(2)
(2)
(2)
SONET/SDH Frequency Select Input/General-Purpose I/O 4. When RST goes high the state
of this pin sets the reset-default state of MCR3:SONSDH, MCR6:DIG1SS, and MCR6:DIG2SS.
After RST goes high, this pin can be used as a general-purpose I/O pin. GPCR:GPIO4D
configures this pin as an input or an output. GPCR:GPIO4O specifies the output value.
GPSR:GPIO4 indicates the state of the pin.
Reset latched values:
Interrupt Request/Loss of Signal. Programmable (default: INTREQ). The INTCR:LOS bit
determines whether the pin indicates interrupt requests or loss of signal (i.e., loss of selected
reference).
INTCR:LOS = 0: INTREQ mode
INTCR:LOS = 1: LOS mode
Chip Select. This pin must be asserted (low) to read or write internal registers.
Serial Clock. SCLK is always driven by the SPI bus master.
Serial Data Input. The SPI bus master transmits data to the device on this pin.
Serial Data Output. The device transmits data to the SPI bus master on this pin.
Clock Phase. See
0 = Data is latched on the leading edge of the SCLK pulse.
1 = Data is latched on the trailing edge of the SCLK pulse.
JTAG Test Reset (Active Low). Asynchronously resets the test access port (TAP) controller. If
not used, JTRST can be held low or high.
JTAG Clock. Shifts data into JTDI on the rising edge and out of JTDO on the falling edge. If
not used, JTCLK can be held low or high.
JTAG Test Data Input. Test instructions and data are clocked in on this pin on the rising edge
of JTCLK. If not used, JTDI can be held low or high.
JTAG Test Data Output. Test instructions and data are clocked out on this pin on the falling
edge of JTCLK. If not used, leave unconnected.
JTAG Test Mode Select. Sampled on the rising edge of JTCLK and is used to place the port
into the various defined IEEE 1149.1 states. If not used connect to VDDIO or leave
unconnected.
0 = SDH rates (N x 2.048MHz)
1 = SONET rates (N x 1.544MHz)
The behavior of this pin is configured in the
active low. Drive action can be push-pull or open drain. The pin can also be configured as
a general-purpose output if the interrupt request function is not needed.
This pin indicates the real-time state of the selected reference activity monitor (see Section
7.5.3).
10.5
10.4
Figure
for timing specifications.
for timing specifications.
7-4.
PIN DESCRIPTION
PIN DESCRIPTION
PIN DESCRIPTION
INTCR
register. Polarity can be active high or
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