MT41J64M16LA-15E IT:B Micron Technology Inc, MT41J64M16LA-15E IT:B Datasheet - Page 171

• Manufacturer Part Number: MT41J64M16LA-15E IT:B
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr

Specifications of MT41J64M16LA-15E IT:B

• Organization: 64Mx16
• Density: 1Gb
• Address Bus: 16b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: -40C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 355mA
• Pin Count: 96
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

Figure 92: WRITE (BL8) to PRECHARGE
Figure 93: WRITE (BC4 Mode Register Setting) to PRECHARGE
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN
DQS, DQS#
DQS, DQS#
Command
Command
Address
Address
DQ BC4
DQ BL8
CK#
CK#
CK
CK
WRITE
WRITE
Valid
Valid
T0
T0
NOP
NOP
T1
T1
Notes:
Notes:
NOP
NOP
T2
T2
1. DI n = data-in from column n.
2. Seven subsequent elements of data-in are applied in the programmed order following
3. Shown for WL = 7 (AL = 0, CWL = 7).
1. NOP commands are shown for ease of illustration; other commands may be valid at
2. The write recovery time (
3. The fixed BC4 setting is activated by MR0[1:0] = 10 during the WRITE command at T0.
4. DI n = data-in for column n.
5. BC4 (fixed), WL = 5, RL = 5.
NOP
NOP
T3
T3
WL = AL + CWL
WL = AL + CWL
DO n.
these times.
write data is shown at T7.
command can be issued to the same bank.
NOP
NOP
T4
T4
NOP
NOP
T5
T5
NOP
NOP
T6
T6
t
171
WR) is referenced from the first rising clock edge after the last
t
WR specifies the last burst WRITE cycle until the PRECHARGE
NOP
NOP
T7
T7
DI
DI
n
n
n + 1
n + 1
DI
DI
Micron Technology, Inc. reserves the right to change products or specifications without notice.
n + 2
n + 2
NOP
NOP
T8
T8
DI
DI
n + 3
n + 3
DI
DI
1Gb: x4, x8, x16 DDR3 SDRAM
NOP
n + 4
NOP
T9
T9
DI
n + 5
DI
Indicates A Break in
Time Scale
Indicates A Break in
Time Scale
T10
NOP
n + 6
T10
NOP
DI
n + 7
DI
NOP
NOP
T11
T11
© 2006 Micron Technology, Inc. All rights reserved.
t WR
Transitioning Data
Transitioning Data
NOP
NOP
T12
T12
t WR
NOP
NOP
Ta0
Ta0
Don’t Care
Don’t Care
Valid
Valid
Ta1
Ta1
PRE
PRE