MT41J64M16LA-15E IT:B Micron Technology Inc, MT41J64M16LA-15E IT:B Datasheet - Page 154

• Manufacturer Part Number: MT41J64M16LA-15E IT:B
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr

Specifications of MT41J64M16LA-15E IT:B

• Organization: 64Mx16
• Density: 1Gb
• Address Bus: 16b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: -40C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 355mA
• Pin Count: 96
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN
ure 71 (page 156). DDR3 SDRAM does not allow interrupting or truncating any READ
burst.
Data from any READ burst must be completed before a subsequent WRITE burst is al-
lowed. An example of a READ burst followed by a WRITE burst for BL8 is shown in
Figure 72 (page 156) (BC4 is shown in Figure 73 (page 157)). To ensure the read data is
completed before the write data is on the bus, the minimum READ-to-WRITE timing is
RL +
A READ burst may be followed by a PRECHARGE command to the same bank provided
auto precharge is not activated. The minimum READ-to-PRECHARGE command spac-
ing to the same bank is four clocks and must also satisfy a minimum analog time from
the READ command. This time is called
cycles later than the READ command. Examples for BL8 are shown in Figure 74
(page 157) and BC4 in Figure 75 (page 158). Following the PRECHARGE command, a
subsequent command to the same bank cannot be issued until
CHARGE command followed by another PRECHARGE command to the same bank is
allowed. However, the precharge period will be determined by the last PRECHARGE
command issued to the bank.
If A10 is HIGH when a READ command is issued, the READ with auto precharge func-
tion is engaged. The DRAM starts an auto precharge operation on the rising edge, which
is AL +
Figure 77 (page 158)). If
auto precharge operation will be delayed until
not satisfied at the edge, the starting point of the auto precharge operation will be de-
layed until
t
clock edge after this event). The time from READ with auto precharge to the next ACTI-
VATE command to the same bank is AL + (
the next integer. In any event, internal precharge does not start earlier than four clocks
after the last 8n-bit prefetch.
RP starts at the point at which the internal precharge happens (not at the next rising
t
CCD - WL + 2
t
RTP cycles after the READ command. DRAM support a
t
RTP (MIN) is satisfied. In case the internal precharge is pushed out by
t
CK.
t
RAS (MIN) is not satisfied at the edge, the starting point of the
154
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
RTP (READ-to-PRECHARGE).
t
RTP +
1Gb: x4, x8, x16 DDR3 SDRAM
t
RAS (MIN) is satisfied. If
t
RP)*, where * means rounded up to
© 2006 Micron Technology, Inc. All rights reserved.
t
t
RAS lockout feature (see
RP is met. The PRE-
READ Operation
t
RTP starts AL
t
RTP (MIN) is
t
RTP,