MT49H64M9CHT-25:A Micron Technology Inc, MT49H64M9CHT-25:A Datasheet - Page 38

• Manufacturer Part Number: MT49H64M9CHT-25:A
• Manufacturer: Micron Technology Inc
• Type: RLDRAMr

Specifications of MT49H64M9CHT-25:A

• Organization: 64Mx9
• Address Bus: 25b
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 675mA
• Pin Count: 144
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

WRITE
Figure 14:
PDF: 09005aef815b2df8/Source: 09005aef811ba111
576Mb_RLDRAM_II_SIO_Core2.fm - Rev. F 6/09 EN
WRITE Command
Write accesses are initiated with a WRITE command, as shown in Figure 14. The address
needs to be provided during the WRITE command.
During WRITE commands, data will be registered at both edges of DK according to the
programmed burst length (BL). The RLDRAM operates with a WRITE latency (WL) that
is one cycle longer than the programmed READ latency (RL + 1), with the first valid data
registered at the first rising DK edge WL cycles after the WRITE command.
Since the input and output data busses are separate, any WRITE burst may be followed
by a subsequent READ command without encountering external data bus contention.
Figure 21 on page 46 illustrates the timing requirements for a WRITE followed by a READ
command.
Setup and hold times for incoming D relative to the DK edges are specified as
t
hold times for the DM signal are also
ADDRESS
ADDRESS
DH. The input data is masked if the corresponding DM signal is HIGH. The setup and
BANK
WE#
REF#
CK#
CS#
CK
576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM II
DON’T CARE
BA
A
38
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DS and
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
DH.
©2004 Micron Technology, Inc. All rights reserved.
Commands
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DS and