MT49H64M9CHT-25:A Micron Technology Inc, MT49H64M9CHT-25:A Datasheet - Page 17

• Manufacturer Part Number: MT49H64M9CHT-25:A
• Manufacturer: Micron Technology Inc
• Type: RLDRAMr

Specifications of MT49H64M9CHT-25:A

• Organization: 64Mx9
• Address Bus: 25b
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 675mA
• Pin Count: 144
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Electrical Specifications – Idd
Table 4:
PDF: 09005aef815b2df8/Source: 09005aef811ba111
576Mb_RLDRAM_II_SIO_D2.fm - Rev. F 6/09 EN
Standby current
Active standby
current
Operational
current
Operational
current
Operational
current
Burst refresh
current
Distributed
refresh current
Operating burst
write current
example
Operating burst
write current
example
Operating burst
write current
example
Operating burst
read current
example
Operating burst
read current
example
Operating burst
read current
example
Description
Idd Operating Conditions and Maximum Limits
Condition
t
CS# = 1; No commands; Bank address
incriminated and half address/data change
once every 4 clock cycles
BL = 2; Sequential bank access; Bank transitions
once every
every
Continuous data during WRITE commands
BL = 4; Sequential bank access; Bank transitions
once every
every
Continuous data during WRITE commands
BL = 8; Sequential bank access; Bank transitions
once every
every
Continuous data during WRITE commands
Eight-bank cyclic refresh; Continuous address/
data; Command bus remains in refresh for all 8
banks
Single-bank refresh; Sequential bank access;
Half address transitions once every
Continuous data
BL = 2; Cyclic bank access; Half of address bits
change every clock cycle; Continuous data;
Measurement is taken during continuous
WRITE
BL = 4; Cyclic bank access; Half of address bits
change every 2 clock cycles; Continuous data;
Measurement is taken during continuous
WRITE
BL = 8; Cyclic bank access; Half of address bits
change every 4 clock cycles; Continuous data;
Measurement is taken during continuous
WRITE
BL = 2; Cyclic bank access; Half of address bits
change every clock cycle; Continuous data;
Measurement is taken during continuous READ
BL = 4; Cyclic bank access; Half of address bits
change every 2 clock cycles; Continuous data;
Measurement is taken during continuous READ
BL = 8; Cyclic bank access; Half of address bits
change every 4 clock cycles; Continuous data;
Measurement is taken during continuous READ
Notes:
CK = idle; All banks idle, no inputs toggling
t
t
t
RC; Read followed by write sequence;
RC; Read followed by write sequence;
RC; Read followed by write sequence;
1. Idd specifications are tested after the device is properly initialized. +0°C ≤ T
2.
3. Input slew rate is specified in Table 7 on page 20.
t
t
t
RC; Half address transitions once
RC; Half address transitions once
RC; Half address transitions once
≤ Vdd ≤ +1.9V, +2.38V ≤ Vext ≤ +2.63V, +1.4V ≤ Vddq ≤ Vdd, Vref = Vddq/2.
t
CK =
t
DK = MIN,
576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM II
t
RC = MIN.
t
RC;
17
Idd2R (Vdd) x9/x18 1225
Idd4R (Vdd) x9/x18
Idd8R (Vdd) x9/x18
Iref1 (Vdd) x9/x18
Iref2 (Vdd) x9/x18
Idd1 (Vdd) x9/x18
Idd2 (Vdd) x9/x18
Idd3 (Vdd) x9/x18
Isb1 (Vdd) x9/x18
Isb2 (Vdd) x9/x18
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Idd2W (Vext)
Idd4W (Vext)
Idd8W (Vext)
Idd2W (Vdd)
Idd4W (Vdd)
Idd8W (Vdd)
Idd2R (Vext)
Idd4R (Vext)
Idd8R (Vext)
Iref1 (Vext)
Iref2 (Vext)
Idd1 (Vext)
Idd2 (Vext)
Idd3 (Vext)
Isb1 (Vext)
Isb2 (Vext)
Symbol
x9/x18
x9/x18
x9/x18
Electrical Specifications – I
1335
-18
365
465
475
505
995
425
985
770
860
655
55
15
15
20
80
20
50
30
30
50
30
30
5
5
©2004 Micron Technology, Inc. All rights reserved.
-25E
293
380
400
430
790
330
980
785
675
865
685
575
53
15
15
20
80
20
50
30
30
50
30
30
5
5
288
348
362
408
785
325
970
779
668
860
680
570
-25
48
15
15
20
80
20
50
30
30
50
30
30
5
5
C
≤ +95°C; +1.7V
233
305
319
368
615
267
819
609
525
735
525
450
-33
48
13
13
18
70
18
40
25
25
40
25
25
5
5
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
DD