MT49H64M9CHT-25:A Micron Technology Inc, MT49H64M9CHT-25:A Datasheet - Page 22

• Manufacturer Part Number: MT49H64M9CHT-25:A
• Manufacturer: Micron Technology Inc
• Type: RLDRAMr

Specifications of MT49H64M9CHT-25:A

• Organization: 64Mx9
• Address Bus: 25b
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 675mA
• Pin Count: 144
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Input Slew Rate Derating
PDF: 09005aef815b2df8/Source: 09005aef811ba111
576Mb_RLDRAM_II_SIO_Core2.fm - Rev. F 6/09 EN
Note:
Table 9 on page 23 and Table 10 on page 24 define the address, command, and data
setup and hold derating values. These values are added to the default
t
the 2 V/ns the nominal setup and hold specifications are based upon.
To determine the setup and hold time needed for a given slew rate, add the
default specification to the “
specification to the “
derated data setup and hold values can be determined in a like manner using the “
Vref to CK/CK# Crossing” and “
derating values on Table 9 and Table 10 apply to all speed grades.
The setup times on Table 9 and Table 10 represent a rising signal. In this case, the time
from which the rising signal crosses Vih(AC) MIN to the CK/CK# cross point is static and
must be maintained across all slew rates. The derated setup timing represents the point
at which the rising signal crosses Vref(DC) to the CK/CK# cross point. This derated value
is calculated by determining the time needed to maintain the given slew rate and the
delta between Vih(AC) MIN and the CK/CK# cross point. The setup values in Table 9 and
Table 10 are also valid for falling signals (with respect to Vil[ac] MAX and the CK/CK#
cross point).
The hold times in Table 9 and Table 10 represent falling signals. In this case, the time
from which the falling signal crosses the CK/CK# cross point to when the signal crosses
Vih(DC) MIN is static and must be maintained across all slew rates. The derated hold
timing represents the delta between the CK/CK# cross point to when the falling signal
crosses Vref(DC). This derated value is calculated by determining the time needed to
maintain the given slew rate and the delta between the CK/CK# cross point and Vih(DC).
The hold values in Table 9 and Table 10 are also valid for rising signals (with respect to
Vil[dc] MAX and the CK and CK# cross point).
AH/
The above descriptions also pertain to data setup and hold derating when CK/CK# are
replaced with DK/DK#.
t
CH/
t
DH specifications when the slew rate of any of these input signals is less than
576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM II
t
AH/
t
CH CK/CK# Crossing to Vref” derated values on Table 9. The
t
AS/
22
t
DH to CK/CK# Crossing to Vref” values on Table 10. The
t
CS Vref to CK/CK# Crossing” and the
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Electrical Specifications – AC and DC
©2004 Micron Technology, Inc. All rights reserved.
t
AS/
t
AH/
t
CS/
t
t
AS/
CH default
t
DS and
t
CS
t
DS