FWLXT9784BE.A3 Cortina Systems Inc, FWLXT9784BE.A3 Datasheet - Page 60

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FWLXT9784BE.A3

Manufacturer Part Number
FWLXT9784BE.A3
Description
Manufacturer
Cortina Systems Inc
Datasheet

Specifications of FWLXT9784BE.A3

Lead Free Status / RoHS Status
Not Compliant

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LXT9784 — Low-Power Octal PHY
5.0
60
1. Refer to
Bit(s)
0.15
0.14
0.13
0.12
0.10
0.11
Table 42. Bit Type Designations
Table 43. Control Register (Register 0) Bit Definitions
Reset
Loopback
Speed Selection
Auto-Negotiation
Enable
Power Down
Isolate
Table 42
Register Definitions
The PHY registers can be accessed through the MII management interface.
Table 42
Name
SC
RO
P
LL
LH
for Type definitions.
Designator
defines the bit type designations used in the following tables.
Sets the status and control register of the PHY to their default states and is self-
clearing. The PHY returns a value of “1” when this register is read until the reset
process has completed and accepts a read or write transaction.
1 = PHY reset.
default 0 = normal operation.
Enable loopback of transmit data to the receive data path. The PHY receive circuitry
is isolated from the network.
Note that this may cause the de-scrambler to lose synchronization and produce 560
ns of “dead time”.
1 = Loopback enabled.
default 0 = Loopback disabled (normal operation).
Controls speed when auto-negotiation is disabled.
default 1 = 100 MBPS
0 = 10 MBPS
Bits 0.13 & 0.8 (Speed Selection and Duplex Mode, respectively) are ignored when
auto-negotiation is enabled.
Bits 4.12:5 (Technology Ability Field) depends on the PHY ability (Register 0) to
define the preferred link configuration.
default 1 = auto-negotiation enable.
0 = auto-negotiation disable.
1 = Analog section only power-down enabled.
default 0 = Power-down disabled (normal operation).
Allows the PHY to isolate the Media Independent Interface. The PHY doesn't
respond on the both transmit and receive activities.
1 = Logical isolate of internal MII interface.
default 0 = Normal operation.
Self Cleared
Read Only
external Pin affects content
Latch Low
Latch High.
Definition
Description
Datasheet
Type
RW
RW
RW
RW
RW
RW
SC
P
P
1

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