FWLXT9784BE.A3 Cortina Systems Inc, FWLXT9784BE.A3 Datasheet - Page 49

• Manufacturer Part Number: FWLXT9784BE.A3
• Manufacturer: Cortina Systems Inc

Specifications of FWLXT9784BE.A3

• Lead Free Status / RoHS Status: Not Compliant

3.3.1
3.4
Datasheet
Figure 13. Typical RMII Application
RMII Clock
In RMII mode of operation, the master input clock (MCLK) frequency should be 50 MHz ± 50
ppm, with a duty-cycle between 35% and 65% inclusive.
SMII Applications
The SMII ports provide eight low pin-count interfaces between the LXT9784’s eight PHYs and an
ASIC switch, as an alternative to the RMII interface. The SMII interface is composed of two
signals per port, a global synchronization signal, and a global reference clock.
LED0_[A:C]
LED1_[A:C]
LED2_[A:C]
LED3_[A:C]
LED4_[A:C]
LED5_[A:C]
LED6_[A:C]
LED7_[A:C]
RBIAS100_0
RBIAS100_1
RBIAS10_0
RBIAS10_1
P0_MDI
P1_MDI
P2_MDI
P3_MDI
P4_MDI
P5_MDI
P6_MDI
P7_MDI
TPOP
ID[1:0]
TPIN
TPON
MDIO
TPIP
MDC
INT
MII Management
Per Port
Analog pins
PHY ID
MDI Ports
LEDs
Interrupt
Interface
LXT9784
Low-Power Octal PHY — LXT9784
Configuration
Interfaces
Test Port
RMII
RMII0_[6:0]
RMII1_[6:0]
RMII2_[6:0]
RMII3_[6:0]
RMII4_[6:0]
RMII5_[6:0]
RMII6_[6:0]
RMII7_[6:0]
MODE[2:0]
SCRMBP
FRCLNK
BP4B5B
RESET
TEXEC
FRC34
TOUT
MCLK
SYNC
MDIX
TCK
TI
CRSDV
RXD[1:0]
TXD[1:0]
TXEN
RXER
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