FWLXT9784BE.A3 Cortina Systems Inc, FWLXT9784BE.A3 Datasheet - Page 36

• Manufacturer Part Number: FWLXT9784BE.A3
• Manufacturer: Cortina Systems Inc

Specifications of FWLXT9784BE.A3

• Lead Free Status / RoHS Status: Not Compliant

LXT9784 — Low-Power Octal PHY
2.4
2.4.1
2.4.1.1
36
Figure 9. RMII Data Transmission
Figure 10. SMII Transmit Data Serial Stream
MCLK
TXENn
TXDn_1
TXDn_0
MCLK
SYNC
TXDn
100BASE-TX SMII Data Transmission
The data is signaled in ten-bit segments, where each segment represents a new byte of data. Each
segment is delimited by a SYNC pulse (every 10 clocks).
When TX_EN in the serial bit stream is de-asserted, then TXD[7:0] are the inter-frame control bits
(for a direct MAC to MAC connection). When the TX_EN bit asserts, the PHY accepts the data
stream on the TXDn line.
10BASE-T Mode
10BASE-T Receiver
10BASE-T Manchester Decoder
The LXT9784 PHYs perform Manchester decoding and timing recovery when in 10BASE-T
mode. The Manchester-encoded data stream is decoded from TPIPn and TPINn to separate
Receive Clock and Receive Data signals from the differential signal. This data is assembled to
nibbles and transferred to the RMII/SMII.
10BASE-T RMII Data Reception
RMII data is transferred in di-bits at a 50 MHz rate. Therefore the data on RXDn_<1:0> is changed
every 10 clock cycles.
0
0
TX_ER
1
0
TX_EN
Preamble
1
0
1
0
TXD0
0
1
Figure 10
Transmit stream direction
TXD1
0
1
shows the format of the SMII transmit serial stream.
0
1
TXD2
SFD
0
1
TXD3
1
1
TXD4
x
x
x
x
TXD5
Data
x
x
TXD6
x
x
x
x
TXD7
0
0
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