FWLXT9784BE.A3 Cortina Systems Inc, FWLXT9784BE.A3 Datasheet - Page 30

• Manufacturer Part Number: FWLXT9784BE.A3
• Manufacturer: Cortina Systems Inc

Specifications of FWLXT9784BE.A3

• Lead Free Status / RoHS Status: Not Compliant

LXT9784 — Low-Power Octal PHY
2.3
2.3.1
2.3.1.1
2.3.1.2
30
Table 11. LXT9784 Modes of Operation
The PHYs can individually auto-negotiate with their link partners, and thereby auto-configure their
speeds of operation. The MDI/MDIX auto-switching configuration is done prior to Auto-
Negotiation.
The RMII or SMII mode is selected by mode select balls MODE<2:0>.
Three balls select the general operation of the device.
different modes of operation.
100BASE-TX Mode
100BASE-TX Receiver
Each receive subsection of the LXT9784 PHYs accepts 100BASE-TX MLT-3 data on TPIPn and
TPINn (where “n” is the port number). Due to the advanced digital signal processing design
techniques employed, the PHYs accurately receive valid data from CAT5 UTP and type 1 STP
cable over distances well in excess of 100 meters.
Digital Adaptive Equalizer
The distorted MLT-3 signal at the end of the wire is restored by the equalizer. The equalizer filter
coefficients are digitally adapted based on the shape of the received signal, equalizing the signal to
exceed IEEE specification bit error rate (BER) performance for transmission over 100 meters of
CAT 5 twisted pair.
Receive Clock and Data Recovery
The clock recovery circuit uses advanced DSP technology to compensate for signal distortion and
jitter. The circuitry recovers the 125 MHz clock and data from the equalizer output and presents the
data to the NRZI-to-NRZ converter.
1. MODE 2 pin must be set to zero for normal operation.
2
0
0
0
0
1
1
1
1
1
Mode Pins
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
Reserved
RMll
SMII
Reserved
Reserved
Reserved
Reserved
Manufacturing
Test Mode
Mode
MII
50 MHz
125 MHz
Frequency
MCLK
Table 11
shows the balls settings for the
Datasheet