FWLXT9784BE.A3 Cortina Systems Inc, FWLXT9784BE.A3 Datasheet - Page 31

• Manufacturer Part Number: FWLXT9784BE.A3
• Manufacturer: Cortina Systems Inc

Specifications of FWLXT9784BE.A3

• Lead Free Status / RoHS Status: Not Compliant

2.3.1.3
2.3.1.4
2.3.1.5
2.3.1.6
2.3.1.7
Datasheet
Baseline Wander Correction
The baseline wander effect is the wandering of the DC offset of the receive signal. The wander of
the DC offset happens when the 100BASE-TX data is not DC-balanced. Baseline wander can
greatly reduce BER performance. The LXT9784 Equalizer has an automatic baseline wander
correction circuit, thereby preserving outstanding BER performance in case of extreme baseline
wander conditions.
Decoder
The LXT9784 PHYs first convert the data from the clock recovery circuitry to NRZ format. The
NRZ serial data stream is assembled to 5-bit symbols, de-scrambled and aligned to symbol
boundaries. The de-scrambling is based on synchronization to the transmitted Idle pattern
generated by an 11-bit LFSR during idle. The data is then decoded at the 5B/4B decoder.
100BASE-TX Receive Framing
The LXT9784 PHYs do not differentiate between the fields of the MAC frame containing
preamble, SFD, data and CRC. During 100 Mbps reception, the PHY detects Start-of-Stream
Delimiter (SSD) (/J/K/) and End-of-Stream Delimiter ESD) (/T/R/) pairs. The PHY strips those
symbols from the data stream before passing the packet to the MAC. CRSDVn is asserted on a
detection of a non-idle symbol.
100BASE-TX RMII Data Reception
When the receive medium is idle, CRSDVn is de-asserted and the data on RXDn_<1:0> is “00”.
When carrier is detected, CRSDVn signal asserts asynchronously. After the internal FIFO is half
full, the PHY transfers two bits of recovered data on RXDn_<1:0> at each clock period,
synchronous to MCLK.
If the PHY has additional bits to present on RXDn_<1:0> (accumulated in the FIFO) after
CRSDVn initial de-assertion, then CRSDVn toggles at 25 MHz, starting on a nibble boundary.
See
If false carrier is detected (bad SSD), then RXDn_<1:0> will be “10” until the end of the receive
event. See
100BASE-TX SMII Data Reception
The data is signaled in ten-bit segments, where each segment represents a new byte of data. Each
segment is delimited by a SYNC pulse (every 10 clocks).
RXD_[7:0] in the serial bit stream are used to convey packet data, receive error status from the
previous frame, and PHY status, decoded by two SMII control bits (CRS and RX_DV). See
12
When the receive medium is busy receiving a frame, SMII control bit CRS is asserted. RX_ER
(inter-frame status bit RXD0) is asserted if during a frame reception the internal FIFO overflows or
underflows.
If false carrier is detected (bad Start-of-Stream Delimiter), then inter-frame status bit RXD6 is
asserted.
for bit definitions.
Figure 5
Figure
6.
Figure 7
shows the SMII receive data stream.
Low-Power Octal PHY — LXT9784
Table
31