FWLXT9784BE.A3 Cortina Systems Inc, FWLXT9784BE.A3 Datasheet - Page 40

• Manufacturer Part Number: FWLXT9784BE.A3
• Manufacturer: Cortina Systems Inc

Specifications of FWLXT9784BE.A3

• Lead Free Status / RoHS Status: Not Compliant

LXT9784 — Low-Power Octal PHY
2.6
2.6.1
2.6.2
2.6.3
2.6.4
40
Table 15. Crossed-over Pin Assignments
Hardware Control Interface
The LXT9784 can be configured for unmanaged applications, using external pins (hardware
control) as described in the following paragraphs.
MDI-X
During RESET, enables the auto-switch feature. If this feature was disabled, then after reset the
MDI-X pin controls the manual MDI/MDI-X switching.
FRCLNK
During RESET:
If FRCLNK was set, then after reset the FRCLNK pin will control speed selection (PHY reg0, bit
13), where:
The FRCLNK pin and bit 11 in PHY register 11’h are ORed together.
FRC34
The FRC34 pin and bit 12 in PHY register 11’h are ORed together.
BP4B5B
To enter 4B/5B bypass mode, this pin must be set high after the end of reset. During reset, this pin
must be pulled down to ensure proper operation of the LXT9784.
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When MDI-X = 1, the MDI port is forced to MDI-X
(cross- over mode).
When MDI-X = 0, the MDI port is forced to MDI
(straight-through mode).
When FRCLNK = 1, it forces good link (PHY reg17, bit 11), link integrity (PHY reg17, bit 1),
and disables auto-negotiation (PHY reg0, bit 12)
When FRCLNK = 0, Normal Operation.
When FRCLNK = 1, it forces 100 Mbps.
When FRCLNK = 0, it forces 10 Mbps.
Contact
(MDI Crossover)
5
6
7
8
(Force 34 Transmit Pattern)
(4B/5B Bypass)
(Force Link)
Not used
TDN_n
Not used
Not used
MDI Signal
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