HBLXT9761HC.C4 Intel, HBLXT9761HC.C4 Datasheet - Page 43

• Manufacturer Part Number: HBLXT9761HC.C4
• Manufacturer: Intel

Specifications of HBLXT9761HC.C4

• Lead Free Status / RoHS Status: Not Compliant

2.10.3
2.10.4
Datasheet
EXTEST
IDCODE
SAMPLE
High Z
Clamp
BYPASS
1. The JEDEC ID is an 8-bit identifier. The MSB is for parity and is ignored.
Intel’s JEDEC ID is FE (1111 1110) which becomes 111 1110.
Version
Table 11. BSR Mode of Operation
Table 12. Supported JTAG Instructions
Table 13. Device ID Register
31:28
0000
Name
Instruction Register
After the state machine resets, the IDCODE instruction is always invoked. The decode logic
ensures the correct data flow to the Data registers according to the current instruction. Valid
instructions are listed in
Boundary Scan Register
Each BSR cell has two stages. A flip-flop and a latch are used for the serial shift stage and the
parallel output stage. There are four modes of operation as listed in
Mode
1
2
3
4
2621 (LXT9761)
2635 (LXT9781)
Part ID (hex)
0000000000000000
1111111111001111
1111111111111110
1111111111111110
1111111111101111
1111111111111111
27:12
Code
Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781
Table
System Function
Description
Capture
12.
Update
External Test
ID Code Inspection
Sample Boundary
Force Float
Clamp
Bypass Scan
Jedec Continuation Characters
Shift
Description
0000
11:8
BSR
BSR
Table
ID REG
Bypass
BSR
Bypass
JEDEC ID
111 1110
11.
7:1
Data Register
1
Reserved
0
1
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