HBLXT9761HC.C4 Intel, HBLXT9761HC.C4 Datasheet - Page 32

• Manufacturer Part Number: HBLXT9761HC.C4
• Manufacturer: Intel

Specifications of HBLXT9761HC.C4

• Lead Free Status / RoHS Status: Not Compliant

LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII
2.6.7
2.7
2.7.1
32
1. An independent RMII port serves each independent Network port. Network port configurations are independently
2. The Scrambler can be bypassed by setting 16.12 = 0.
D0
D1
Figure 14. RMII Data Flow
selectable.
Reduced MII Mode Data Flow
di-bit
pairs
D0
D1
Parallel
Parallel
4B/5B Coding Operations
The 100BASE-X protocol specifies the use of a 5-bit symbol code on the network media.
However, data is normally transmitted across the RMII interface in 2-bit nibblets or “di-bits”. The
LXT97x1 incorporates a parallel/serial converter that translates between di-bit pairs and 4-bit
nibbles, and a 4B/5B encoder/decoder circuit that translates between 4-bit nibbles and 5-bit
symbols for the 100BASE-X connection.
symbols.
Serial
Serial
100 Mbps Operation
100BASE-X Network Operations
During 100BASE-X operation, the LXT97x1 transmits and receives 5-bit symbols across the
network link.
actively transmitting data, the LXT97x1 sends out Idle symbols on the line.
In 100TX mode, the LXT97x1 scrambles the data and transmits it to the network using MLT-3 line
code. The MLT-3 signals received from the network are descrambled and decoded and sent across
the RMII to the MAC.
In 100FX mode, the LXT97x1 transmits and receives NRZI signals across the PECL interface. An
external 100FX transceiver module is required to complete the fiber connection.
As shown in
LXT97x1 detects the start of preamble, it transmits a J/K Start of Stream Delimiter (SSD) symbol
to the network. It then encodes and transmits the rest of the packet, including the balance of the
preamble, the Start of Frame Delimiter (SFD), packet data, and CRC. Once the packet ends, the
LXT97x1 transmits the T/R End of Stream Delimiter (ESD) symbol and then returns to
transmitting Idle symbols.
to
to
D0 D1 D2 D3
Table 10 on page 34
Figure
Figure 15
nibbles
4-bit
15, the MAC starts each transmission with a preamble pattern. As soon as the
shows the structure of a standard frame packet. When the MAC is not
4B/5B
shows 4B/5B symbol coding (not all symbols are valid).
S0 S1 S2 S3 S4
Figure 14
symbols
5-bit
shows the data conversion flow from nibbles to
Scramble
Scramble
De-
MLT3
pattern: 0, +1, 0, -1, 0, +1...
All transitions must follow
0
No Transition = 0.
Transition = 1.
+1
Datasheet
0
-1
0