HBLXT9761HC.C4 Intel, HBLXT9761HC.C4 Datasheet - Page 26

• Manufacturer Part Number: HBLXT9761HC.C4
• Manufacturer: Intel

Specifications of HBLXT9761HC.C4

• Lead Free Status / RoHS Status: Not Compliant

LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII
2.3.2
2.3.2.1
2.4
2.4.1
2.4.2
26
As a matter of good practice, these supplies should be as clean as possible. Typical filtering and
decoupling are shown in
Clock Requirements
Reference Clock
The LXT97x1 requires a constant 50 MHz reference clock (REFCLK). The reference clock is used
to generate transmit signals and recover receive signals. A crystal-based clock is recommended
over a derived clock (i.e, PLL-based) to minmize transmit jitter. Refer to
clock timing requirements.
Initialization
When the LXT97x1 is first powered on, reset, or encounters a link failure state, it checks the MDIO
register configuration bits to determine the line speed and operating conditions to use for the
network link. The configuration bits may be set by the Hardware Control or MDIO interface as
shown in
MDIO Control Mode
In the MDIO Control mode, the LXT97x1 reads the Hardware Control Interface pins to set the
initial (default) values of the MDIO registers. Once the initial values are set, bit control reverts to
the MDIO interface.
Hardware Control Mode
In the Hardware Control Mode, LXT97x1 disables direct write operations to the MDIO registers
via the MDIO Interface. On power-up or hardware reset the LXT97x1 reads the Hardware Control
Interface pins and sets the MDIO registers accordingly.
The following modes are available using either Hardware Control or MDIO Control:
When the network link is forced to a specific configuration, the LXT97x1 immediately begins
operating the network interface as commanded. When auto-negotiation is enabled, the LXT97x1
begins the auto-negotiation / parallel-detection operation.
•
•
•
Force network link to 100FX (Fiber).
Force network link operation to:
100TX, Full-Duplex.
100TX, Half-Duplex.
10BASE-T, Full-Duplex.
10BASE-T, Half-Duplex.
Allow auto-negotiation / parallel-detection.
Figure
10.
Figure 21 on page
47.
Table 19 on page 53
Datasheet
for