HBLXT9761HC.C4 Intel, HBLXT9761HC.C4 Datasheet - Page 3

• Manufacturer Part Number: HBLXT9761HC.C4
• Manufacturer: Intel

Specifications of HBLXT9761HC.C4

• Lead Free Status / RoHS Status: Not Compliant

Contents
1.0
2.0
Datasheet
Pin Assignments and Signal Descriptions
Functional Description
2.1
2.2
2.3
2.4
2.5
2.6
2.7
Introduction..........................................................................................................21
2.1.1
2.1.2
Interface Descriptions..........................................................................................22
2.2.1
2.2.2
2.2.3
Operating Requirements .....................................................................................25
2.3.1
2.3.2
Initialization..........................................................................................................26
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
Link Establishment ..............................................................................................29
2.5.1
2.5.2
RMII Operation ....................................................................................................30
2.6.1
2.6.2
2.6.3
2.6.4
2.6.5
2.6.6
2.6.7
100 Mbps Operation............................................................................................32
2.7.1
2.7.2
Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781
OSP™ Architecture ................................................................................21
Comprehensive Functionality .................................................................21
10/100 Network Interface .......................................................................22
2.2.1.1 Twisted-Pair Interface ...............................................................22
2.2.1.2 Fiber Interface ...........................................................................23
RMII Interface.........................................................................................23
Configuration Management Interface .....................................................23
2.2.3.1 MDIO Management Interface ....................................................23
2.2.3.2 Hardware Control Interface .......................................................25
Power Requirements..............................................................................25
Clock Requirements ...............................................................................26
2.3.2.1 Reference Clock ........................................................................26
MDIO Control Mode ...............................................................................26
Hardware Control Mode .........................................................................26
Power-Down Mode.................................................................................27
2.4.3.1 Global (Hardware) Power Down................................................27
2.4.3.2 Port (Software) Power Down .....................................................27
Reset ......................................................................................................28
Hardware Configuration Settings ...........................................................28
Auto-Negotiation.....................................................................................29
2.5.1.1 Base Page Exchange................................................................29
2.5.1.2 Next Page Exchange.................................................................29
2.5.1.3 Controlling Auto-Negotiation .....................................................29
Parallel Detection ...................................................................................30
Reference Clock.....................................................................................31
Transmit Enable .....................................................................................31
Carrier Sense & Data Valid ....................................................................31
Receive Error .........................................................................................31
Loopback................................................................................................31
Out of Band Signalling............................................................................31
4B/5B Coding Operations.......................................................................32
100BASE-X Network Operations ...........................................................32
100BASE-X Protocol Sublayer Operations ............................................33
2.7.2.1 PCS Sublayer ............................................................................33
2.7.2.2 PMA Sublayer ...........................................................................35
2.7.2.3 Twisted-Pair PMD Sublayer ......................................................36
2.7.2.4 Fiber PMD Sublayer ..................................................................37
...........................................................................................21
....................................................10
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