HBLXT9761HC.C4 Intel, HBLXT9761HC.C4 Datasheet - Page 27

• Manufacturer Part Number: HBLXT9761HC.C4
• Manufacturer: Intel

Specifications of HBLXT9761HC.C4

• Lead Free Status / RoHS Status: Not Compliant

2.4.3
2.4.3.1
2.4.3.2
Datasheet
Figure 10. Initialization Sequence
Power-Down Mode
The LXT97x1 offers both global and per-port power-down modes.
Global (Hardware) Power Down
The global power-down mode is controlled by PWRDWN pin 82 (PQFP) or W12 (PBGA). When
PWRDWN is High, the following conditions are true:
Port (Software) Power Down
Individual port power-down control is provided by bit 0.11 in the respective port Control Registers
(refer to
true:
•
•
•
•
•
•
•
•
All LXT97x1 ports and clock are shut down.
All outputs are tri-stated.
All weak pad pull-up and pull-down resistors are disabled.
The MDIO registers are not accessible.
The MDIO registers are reset after power down.
The individual port is shut down.
The MDIO registers remain accessible.
The MDIO registers are unaffected.
Reset MDIO Registers to
Control Interface at last
Interface (Read/Write)
Pass Control to MDIO
MDIO Control
Table 35 on page
values read at H/W
Hardware Reset
Mode
Software
Reset?
Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781
Yes
Low
Initialize MDIO Registers
Power-up or Reset
Read H/W Control
MDDIS Voltage
65). During individual port power-down, the following conditions are
Interface
Level?
Disable MDIO Read and
High
Hardware Control
Write Operations
Mode
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