82P2284BB IDT, Integrated Device Technology Inc, 82P2284BB Datasheet - Page 89

• Manufacturer Part Number: 82P2284BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2284BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

from the TSIGn/MTSIGA (MTSIGB) pins on a per-channel/per-TS basis
or on a global basis of the corresponding link. The processed signaling
bits will be inserted to the data stream to be transmitted if frame is
generated. The methods are arranged from the highest to the lowest in
priority:
by specifying the address in the ADDRESS[6:0] bits. Whether the data is
read from or written into the specified indirect register is determined by
the RWN bit and the data is in the D[7:0] bits. The access status is indi-
cated in the BUSY bit. Refer to Chapter 4.5 Indirect Register Access
Scheme for details about the indirect registers write/read access.
Functional Description
IDT82P2284
The following methods can be executed on the signaling bits input
• Selected by the ABXX bit, the signaling bits can be valid in the
• Enabled by the SIGSNAP bit, the signaling snapshot will be exe-
• Enabled by the GSTRKEN bit, the signaling bits (ABCD) of all
The indirect registers of the Transmit Payload Control are accessed
upper 2-bit positions of the lower nibble of each channel or in the
lower nibble of each channel. The other bits of the channel are
Don’t Care conditions. This function is only supported in T1/J1
mode ESF/SLC-96 format.
cuted. The signaling snapshot means that the signaling bits of the
first basic frame are locked and output as the signaling bits of the
current whole multi-frame. This function is not supported in T1 DM
format.
channels/timeslots of the corresponding link will be replaced by the
signaling trunk conditioning code in the A,B,C,D bits. When the
GSTRKEN bit is ‘0’, the replacement can be performed on a per-
channel/per-TS basis by setting the STRKEN bit in the corre-
sponding channel/timeslot.
89
Table 45: Related Bit / Register In Chapter 3.19
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Note:
* ID means Indirect Register in the Transmit Payload Control function block.
SIGINS (T1/J1 only)
ABXX (T1/J1 only)
PRBSMODE[1:0]
ZCS[2:0] (T1/J1
ADDRESS[6:0]
GSUBST[2:0]
SUBST[2:0]
GSTRKEN
DTRK[7:0]
PRBSDIR
SIGSNAP
TESTEN
STRKEN
A,B,C,D
PCCE
BUSY
TEST
D[7:0]
OINV
RWN
SINV
EINV
only)
Bit
ID * - Signaling Trunk Condi-
T1/J1) / Timeslot Control (for
ID * - Data Trunk Condition-
TPLC / RPLC / PRGD Test
ID * - Channel Control (for
TPLC Access Control
TPLC Control Enable
TPLC Access Status
TPLC Configuration
TPLC Access Data
Configuration
tioning Code
Register
ing Code
E1)
February 25, 2008
TPLC ID * - 41~58 (for
TPLC ID * - 21~38 (for
TPLC ID * - 01~18 (for
0CC, 1CC, 2CC, 3CC
0CB, 1CB, 2CB, 3CB
0CA, 1CA, 2CA, 3CA
0C7, 1C7, 2C7, 3C7
0C9, 1C9, 2C9, 3C9
0C8, 1C8, 2C8, 3C8
T1/J1) / 20~3F (for
T1/J1) / 00~1F (for
T1/J1) / 41~4F &
Address (Hex)
51~5F (for E1)
E1)
E1)